From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753845AbcBALmN (ORCPT ); Mon, 1 Feb 2016 06:42:13 -0500 Received: from terminus.zytor.com ([198.137.202.10]:57304 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753663AbcBALmK (ORCPT ); Mon, 1 Feb 2016 06:42:10 -0500 Date: Mon, 1 Feb 2016 03:41:12 -0800 From: tip-bot for Aravind Gopalakrishnan Message-ID: Cc: tony.luck@intel.com, mingo@kernel.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, linux-edac@vger.kernel.org, peterz@infradead.org, bp@alien8.de, Aravind.Gopalakrishnan@amd.com, hpa@zytor.com, torvalds@linux-foundation.org, bp@suse.de Reply-To: torvalds@linux-foundation.org, hpa@zytor.com, bp@suse.de, Aravind.Gopalakrishnan@amd.com, linux-edac@vger.kernel.org, tglx@linutronix.de, bp@alien8.de, peterz@infradead.org, tony.luck@intel.com, mingo@kernel.org, linux-kernel@vger.kernel.org In-Reply-To: <1453750913-4781-6-git-send-email-bp@alien8.de> References: <1453750913-4781-6-git-send-email-bp@alien8.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce/AMD: Reduce number of blocks scanned per bank Git-Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 60f116fca162d9488f783f5014779463243ab7a2 Gitweb: http://git.kernel.org/tip/60f116fca162d9488f783f5014779463243ab7a2 Author: Aravind Gopalakrishnan AuthorDate: Mon, 25 Jan 2016 20:41:50 +0100 Committer: Ingo Molnar CommitDate: Mon, 1 Feb 2016 10:53:57 +0100 x86/mce/AMD: Reduce number of blocks scanned per bank >>From Fam17h onwards, the number of extended MCx_MISC register blocks is reduced to 4. It is an architectural change from what we had on earlier processors. Although theoritically the total number of extended MCx_MISC registers was 8 in earlier processor families, in practice we only had to use the extra registers for MC4. And only 2 of those were used. So this change does not affect older processors. Tested on Fam10h and Fam15h systems. Signed-off-by: Aravind Gopalakrishnan Signed-off-by: Borislav Petkov Cc: Borislav Petkov Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/1453750913-4781-6-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 3068ce2..5982227 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -28,7 +28,7 @@ #include #include -#define NR_BLOCKS 9 +#define NR_BLOCKS 5 #define THRESHOLD_MAX 0xFFF #define INT_TYPE_APIC 0x00020000 #define MASK_VALID_HI 0x80000000