From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758140AbcIMNcO (ORCPT ); Tue, 13 Sep 2016 09:32:14 -0400 Received: from terminus.zytor.com ([198.137.202.10]:39326 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754866AbcIMNcL (ORCPT ); Tue, 13 Sep 2016 09:32:11 -0400 Date: Tue, 13 Sep 2016 06:31:52 -0700 From: tip-bot for Yazen Ghannam Message-ID: Cc: tglx@linutronix.de, Yazen.Ghannam@amd.com, hpa@zytor.com, mingo@kernel.org, bp@suse.de, linux-kernel@vger.kernel.org Reply-To: Yazen.Ghannam@amd.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, bp@suse.de, hpa@zytor.com, mingo@kernel.org In-Reply-To: <1472737486-1720-1-git-send-email-Yazen.Ghannam@amd.com> References: <1472737486-1720-1-git-send-email-Yazen.Ghannam@amd.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems Git-Commit-ID: 66ef269dbbe45e264ccf7146d5db32b04478d148 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 66ef269dbbe45e264ccf7146d5db32b04478d148 Gitweb: http://git.kernel.org/tip/66ef269dbbe45e264ccf7146d5db32b04478d148 Author: Yazen Ghannam AuthorDate: Mon, 12 Sep 2016 09:59:36 +0200 Committer: Thomas Gleixner CommitDate: Tue, 13 Sep 2016 15:23:11 +0200 x86/mce/AMD: Ensure the deferred error interrupt is of type APIC on SMCA systems The Deferred Error Interrupt Type is set per bank on Scalable MCA systems. This is done in a bitfield in the MCA_CONFIG register of each bank. We should set its type to APIC-based interrupt and not assume BIOS has set it for us. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov Link: http://lkml.kernel.org/r/1472737486-1720-1-git-send-email-Yazen.Ghannam@amd.com Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 0f9d078..16766e0 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -463,6 +463,20 @@ prepare_threshold_block(unsigned int bank, unsigned int block, u32 addr, */ smca_high &= ~BIT(2); + /* + * SMCA sets the Deferred Error Interrupt type per bank. + * + * MCA_CONFIG[DeferredIntTypeSupported] is bit 5, and tells us + * if the DeferredIntType bit field is available. + * + * MCA_CONFIG[DeferredIntType] is bits [38:37] ([6:5] in the + * high portion of the MSR). OS should set this to 0x1 to enable + * APIC based interrupt. First, check that no interrupt has been + * set. + */ + if ((smca_low & BIT(5)) && !((smca_high >> 5) & 0x3)) + smca_high |= BIT(5); + wrmsr(smca_addr, smca_low, smca_high); }