From: tip-bot for Yazen Ghannam <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: tglx@linutronix.de, hpa@zytor.com, mingo@kernel.org,
linux-kernel@vger.kernel.org, Yazen.Ghannam@amd.com, bp@suse.de
Subject: [tip:ras/core] x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks()
Date: Tue, 13 Sep 2016 06:28:07 -0700 [thread overview]
Message-ID: <tip-74ab0e7a836a7df772af50cac21267eb43688841@git.kernel.org> (raw)
In-Reply-To: <1468269447-8808-1-git-send-email-Yazen.Ghannam@amd.com>
Commit-ID: 74ab0e7a836a7df772af50cac21267eb43688841
Gitweb: http://git.kernel.org/tip/74ab0e7a836a7df772af50cac21267eb43688841
Author: Yazen Ghannam <Yazen.Ghannam@amd.com>
AuthorDate: Mon, 12 Sep 2016 09:59:27 +0200
Committer: Thomas Gleixner <tglx@linutronix.de>
CommitDate: Tue, 13 Sep 2016 15:23:06 +0200
x86/mce/AMD: Use msr_ops.misc() in allocate_threshold_blocks()
Change MSR_IA32_MCx_MISC() macro to msr_ops.misc() because SMCA machines
define a different set of MSRs and msr_ops will give you the correct
MISC register.
Signed-off-by: Yazen Ghannam <Yazen.Ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/1468269447-8808-1-git-send-email-Yazen.Ghannam@amd.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
arch/x86/kernel/cpu/mcheck/mce_amd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 7b7f3be..78b7681 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -869,7 +869,7 @@ static int threshold_create_bank(unsigned int cpu, unsigned int bank)
}
}
- err = allocate_threshold_blocks(cpu, bank, 0, MSR_IA32_MCx_MISC(bank));
+ err = allocate_threshold_blocks(cpu, bank, 0, msr_ops.misc(bank));
if (!err)
goto out;
parent reply other threads:[~2016-09-13 13:28 UTC|newest]
Thread overview: expand[flat|nested] mbox.gz Atom feed
[parent not found: <1468269447-8808-1-git-send-email-Yazen.Ghannam@amd.com>]
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