From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752258AbdGYN7b (ORCPT ); Tue, 25 Jul 2017 09:59:31 -0400 Received: from terminus.zytor.com ([65.50.211.136]:38075 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751872AbdGYN71 (ORCPT ); Tue, 25 Jul 2017 09:59:27 -0400 Date: Tue, 25 Jul 2017 06:55:34 -0700 From: tip-bot for Yazen Ghannam Message-ID: Cc: bp@suse.de, torvalds@linux-foundation.org, peterz@infradead.org, tony.luck@intel.com, tglx@linutronix.de, jack@codezen.org, mingo@kernel.org, yazen.ghannam@amd.com, hpa@zytor.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Reply-To: tony.luck@intel.com, jack@codezen.org, tglx@linutronix.de, bp@suse.de, peterz@infradead.org, torvalds@linux-foundation.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, yazen.ghannam@amd.com, mingo@kernel.org, hpa@zytor.com In-Reply-To: <20170724101228.17326-4-bp@alien8.de> References: <20170724101228.17326-4-bp@alien8.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce/AMD: Allow any CPU to initialize the smca_banks array Git-Commit-ID: 9662d43f523dfc0dc242ec29c2921c43898d6ae5 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: 9662d43f523dfc0dc242ec29c2921c43898d6ae5 Gitweb: http://git.kernel.org/tip/9662d43f523dfc0dc242ec29c2921c43898d6ae5 Author: Yazen Ghannam AuthorDate: Mon, 24 Jul 2017 12:12:28 +0200 Committer: Ingo Molnar CommitDate: Tue, 25 Jul 2017 15:50:53 +0200 x86/mce/AMD: Allow any CPU to initialize the smca_banks array Current SMCA implementations have the same banks on each CPU with the non-core banks only visible to a "master thread" on each die. Practically, this means the smca_banks array, which describes the banks, only needs to be populated once by a single master thread. CPU 0 seemed like a good candidate to do the populating. However, it's possible that CPU 0 is not enabled in which case the smca_banks array won't be populated. Rather than try to figure out another master thread to do the populating, we should just allow any CPU to populate the array. Drop the CPU 0 check and return early if the bank was already initialized. Also, drop the WARNing about an already initialized bank, since this will be a common, expected occurrence. The smca_banks array is only populated at boot time and CPUs are brought online sequentially. So there's no need for locking around the array. If the first CPU up is a master thread, then it will populate the array with all banks, core and non-core. Every CPU afterwards will return early. If the first CPU up is not a master thread, then it will populate the array with all core banks. The first CPU afterwards that is a master thread will skip populating the core banks and continue populating the non-core banks. Signed-off-by: Yazen Ghannam Signed-off-by: Borislav Petkov Acked-by: Jack Miller Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/20170724101228.17326-4-bp@alien8.de Signed-off-by: Ingo Molnar --- arch/x86/kernel/cpu/mcheck/mce_amd.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c index 9e314bc..5ce1a56 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_amd.c +++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c @@ -201,8 +201,8 @@ static void smca_configure(unsigned int bank, unsigned int cpu) wrmsr(smca_config, low, high); } - /* Collect bank_info using CPU 0 for now. */ - if (cpu) + /* Return early if this bank was already initialized. */ + if (smca_banks[bank].hwid) return; if (rdmsr_safe_on_cpu(cpu, MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { @@ -216,11 +216,6 @@ static void smca_configure(unsigned int bank, unsigned int cpu) for (i = 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { s_hwid = &smca_hwid_mcatypes[i]; if (hwid_mcatype == s_hwid->hwid_mcatype) { - - WARN(smca_banks[bank].hwid, - "Bank %s already initialized!\n", - smca_get_name(s_hwid->bank_type)); - smca_banks[bank].hwid = s_hwid; smca_banks[bank].id = low; smca_banks[bank].sysfs_id = s_hwid->count++; From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [tip:ras/core] x86/mce/AMD: Allow any CPU to initialize the smca_banks array From: tip-bot for Borislav Petkov Message-Id: Date: Tue, 25 Jul 2017 06:55:34 -0700 To: linux-tip-commits@vger.kernel.org Cc: bp@suse.de, torvalds@linux-foundation.org, peterz@infradead.org, tony.luck@intel.com, tglx@linutronix.de, jack@codezen.org, mingo@kernel.org, yazen.ghannam@amd.com, hpa@zytor.com, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org List-ID: Q29tbWl0LUlEOiAgOTY2MmQ0M2Y1MjNkZmMwZGMyNDJlYzI5YzI5MjFjNDM4OThkNmFlNQpHaXR3 ZWI6ICAgICBodHRwOi8vZ2l0Lmtlcm5lbC5vcmcvdGlwLzk2NjJkNDNmNTIzZGZjMGRjMjQyZWMy OWMyOTIxYzQzODk4ZDZhZTUKQXV0aG9yOiAgICAgWWF6ZW4gR2hhbm5hbSA8eWF6ZW4uZ2hhbm5h bUBhbWQuY29tPgpBdXRob3JEYXRlOiBNb24sIDI0IEp1bCAyMDE3IDEyOjEyOjI4ICswMjAwCkNv bW1pdHRlcjogIEluZ28gTW9sbmFyIDxtaW5nb0BrZXJuZWwub3JnPgpDb21taXREYXRlOiBUdWUs IDI1IEp1bCAyMDE3IDE1OjUwOjUzICswMjAwCgp4ODYvbWNlL0FNRDogQWxsb3cgYW55IENQVSB0 byBpbml0aWFsaXplIHRoZSBzbWNhX2JhbmtzIGFycmF5CgpDdXJyZW50IFNNQ0EgaW1wbGVtZW50 YXRpb25zIGhhdmUgdGhlIHNhbWUgYmFua3Mgb24gZWFjaCBDUFUgd2l0aCB0aGUKbm9uLWNvcmUg YmFua3Mgb25seSB2aXNpYmxlIHRvIGEgIm1hc3RlciB0aHJlYWQiIG9uIGVhY2ggZGllLiBQcmFj dGljYWxseSwKdGhpcyBtZWFucyB0aGUgc21jYV9iYW5rcyBhcnJheSwgd2hpY2ggZGVzY3JpYmVz IHRoZSBiYW5rcywgb25seSBuZWVkcyB0bwpiZSBwb3B1bGF0ZWQgb25jZSBieSBhIHNpbmdsZSBt YXN0ZXIgdGhyZWFkLgoKQ1BVIDAgc2VlbWVkIGxpa2UgYSBnb29kIGNhbmRpZGF0ZSB0byBkbyB0 aGUgcG9wdWxhdGluZy4gSG93ZXZlciwgaXQncwpwb3NzaWJsZSB0aGF0IENQVSAwIGlzIG5vdCBl bmFibGVkIGluIHdoaWNoIGNhc2UgdGhlIHNtY2FfYmFua3MgYXJyYXkgd29uJ3QKYmUgcG9wdWxh dGVkLgoKUmF0aGVyIHRoYW4gdHJ5IHRvIGZpZ3VyZSBvdXQgYW5vdGhlciBtYXN0ZXIgdGhyZWFk IHRvIGRvIHRoZSBwb3B1bGF0aW5nLAp3ZSBzaG91bGQganVzdCBhbGxvdyBhbnkgQ1BVIHRvIHBv cHVsYXRlIHRoZSBhcnJheS4KCkRyb3AgdGhlIENQVSAwIGNoZWNrIGFuZCByZXR1cm4gZWFybHkg aWYgdGhlIGJhbmsgd2FzIGFscmVhZHkgaW5pdGlhbGl6ZWQuCkFsc28sIGRyb3AgdGhlIFdBUk5p bmcgYWJvdXQgYW4gYWxyZWFkeSBpbml0aWFsaXplZCBiYW5rLCBzaW5jZSB0aGlzIHdpbGwKYmUg YSBjb21tb24sIGV4cGVjdGVkIG9jY3VycmVuY2UuCgpUaGUgc21jYV9iYW5rcyBhcnJheSBpcyBv bmx5IHBvcHVsYXRlZCBhdCBib290IHRpbWUgYW5kIENQVXMgYXJlIGJyb3VnaHQKb25saW5lIHNl cXVlbnRpYWxseS4gU28gdGhlcmUncyBubyBuZWVkIGZvciBsb2NraW5nIGFyb3VuZCB0aGUgYXJy YXkuCgpJZiB0aGUgZmlyc3QgQ1BVIHVwIGlzIGEgbWFzdGVyIHRocmVhZCwgdGhlbiBpdCB3aWxs IHBvcHVsYXRlIHRoZSBhcnJheQp3aXRoIGFsbCBiYW5rcywgY29yZSBhbmQgbm9uLWNvcmUuIEV2 ZXJ5IENQVSBhZnRlcndhcmRzIHdpbGwgcmV0dXJuCmVhcmx5LiBJZiB0aGUgZmlyc3QgQ1BVIHVw IGlzIG5vdCBhIG1hc3RlciB0aHJlYWQsIHRoZW4gaXQgd2lsbCBwb3B1bGF0ZQp0aGUgYXJyYXkg d2l0aCBhbGwgY29yZSBiYW5rcy4gVGhlIGZpcnN0IENQVSBhZnRlcndhcmRzIHRoYXQgaXMgYSBt YXN0ZXIKdGhyZWFkIHdpbGwgc2tpcCBwb3B1bGF0aW5nIHRoZSBjb3JlIGJhbmtzIGFuZCBjb250 aW51ZSBwb3B1bGF0aW5nIHRoZQpub24tY29yZSBiYW5rcy4KClNpZ25lZC1vZmYtYnk6IFlhemVu IEdoYW5uYW0gPHlhemVuLmdoYW5uYW1AYW1kLmNvbT4KU2lnbmVkLW9mZi1ieTogQm9yaXNsYXYg UGV0a292IDxicEBzdXNlLmRlPgpBY2tlZC1ieTogSmFjayBNaWxsZXIgPGphY2tAY29kZXplbi5v cmc+CkNjOiBMaW51cyBUb3J2YWxkcyA8dG9ydmFsZHNAbGludXgtZm91bmRhdGlvbi5vcmc+CkNj OiBQZXRlciBaaWpsc3RyYSA8cGV0ZXJ6QGluZnJhZGVhZC5vcmc+CkNjOiBUaG9tYXMgR2xlaXhu ZXIgPHRnbHhAbGludXRyb25peC5kZT4KQ2M6IFRvbnkgTHVjayA8dG9ueS5sdWNrQGludGVsLmNv bT4KQ2M6IGxpbnV4LWVkYWMgPGxpbnV4LWVkYWNAdmdlci5rZXJuZWwub3JnPgpMaW5rOiBodHRw Oi8vbGttbC5rZXJuZWwub3JnL3IvMjAxNzA3MjQxMDEyMjguMTczMjYtNC1icEBhbGllbjguZGUK U2lnbmVkLW9mZi1ieTogSW5nbyBNb2xuYXIgPG1pbmdvQGtlcm5lbC5vcmc+Ci0tLQogYXJjaC94 ODYva2VybmVsL2NwdS9tY2hlY2svbWNlX2FtZC5jIHwgOSArKy0tLS0tLS0KIDEgZmlsZSBjaGFu Z2VkLCAyIGluc2VydGlvbnMoKyksIDcgZGVsZXRpb25zKC0pCgotLQpUbyB1bnN1YnNjcmliZSBm cm9tIHRoaXMgbGlzdDogc2VuZCB0aGUgbGluZSAidW5zdWJzY3JpYmUgbGludXgtZWRhYyIgaW4K dGhlIGJvZHkgb2YgYSBtZXNzYWdlIHRvIG1ham9yZG9tb0B2Z2VyLmtlcm5lbC5vcmcKTW9yZSBt YWpvcmRvbW8gaW5mbyBhdCAgaHR0cDovL3ZnZXIua2VybmVsLm9yZy9tYWpvcmRvbW8taW5mby5o dG1sCgpkaWZmIC0tZ2l0IGEvYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNlX2FtZC5jIGIv YXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNlX2FtZC5jCmluZGV4IDllMzE0YmMuLjVjZTFh NTYgMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9hbWQuYworKysg Yi9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2VfYW1kLmMKQEAgLTIwMSw4ICsyMDEsOCBA QCBzdGF0aWMgdm9pZCBzbWNhX2NvbmZpZ3VyZSh1bnNpZ25lZCBpbnQgYmFuaywgdW5zaWduZWQg aW50IGNwdSkKIAkJd3Jtc3Ioc21jYV9jb25maWcsIGxvdywgaGlnaCk7CiAJfQogCi0JLyogQ29s bGVjdCBiYW5rX2luZm8gdXNpbmcgQ1BVIDAgZm9yIG5vdy4gKi8KLQlpZiAoY3B1KQorCS8qIFJl dHVybiBlYXJseSBpZiB0aGlzIGJhbmsgd2FzIGFscmVhZHkgaW5pdGlhbGl6ZWQuICovCisJaWYg KHNtY2FfYmFua3NbYmFua10uaHdpZCkKIAkJcmV0dXJuOwogCiAJaWYgKHJkbXNyX3NhZmVfb25f Y3B1KGNwdSwgTVNSX0FNRDY0X1NNQ0FfTUN4X0lQSUQoYmFuayksICZsb3csICZoaWdoKSkgewpA QCAtMjE2LDExICsyMTYsNiBAQCBzdGF0aWMgdm9pZCBzbWNhX2NvbmZpZ3VyZSh1bnNpZ25lZCBp bnQgYmFuaywgdW5zaWduZWQgaW50IGNwdSkKIAlmb3IgKGkgPSAwOyBpIDwgQVJSQVlfU0laRShz bWNhX2h3aWRfbWNhdHlwZXMpOyBpKyspIHsKIAkJc19od2lkID0gJnNtY2FfaHdpZF9tY2F0eXBl c1tpXTsKIAkJaWYgKGh3aWRfbWNhdHlwZSA9PSBzX2h3aWQtPmh3aWRfbWNhdHlwZSkgewotCi0J CQlXQVJOKHNtY2FfYmFua3NbYmFua10uaHdpZCwKLQkJCSAgICAgIkJhbmsgJXMgYWxyZWFkeSBp bml0aWFsaXplZCFcbiIsCi0JCQkgICAgIHNtY2FfZ2V0X25hbWUoc19od2lkLT5iYW5rX3R5cGUp KTsKLQogCQkJc21jYV9iYW5rc1tiYW5rXS5od2lkID0gc19od2lkOwogCQkJc21jYV9iYW5rc1ti YW5rXS5pZCA9IGxvdzsKIAkJCXNtY2FfYmFua3NbYmFua10uc3lzZnNfaWQgPSBzX2h3aWQtPmNv dW50Kys7Cg==