From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753529AbeDZTqC (ORCPT ); Thu, 26 Apr 2018 15:46:02 -0400 Received: from terminus.zytor.com ([198.137.202.136]:58009 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751588AbeDZTqA (ORCPT ); Thu, 26 Apr 2018 15:46:00 -0400 Date: Thu, 26 Apr 2018 12:45:48 -0700 From: "tip-bot for jacek.tomaka@poczta.fm" Message-ID: Cc: linux-kernel@vger.kernel.org, jacek.tomaka@poczta.fm, mingo@kernel.org, tglx@linutronix.de, hpa@zytor.com Reply-To: tglx@linutronix.de, hpa@zytor.com, mingo@kernel.org, linux-kernel@vger.kernel.org, jacek.tomaka@poczta.fm In-Reply-To: <20180423161425.24366-1-jacekt@dugeo.com> References: <20180423161425.24366-1-jacekt@dugeo.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/urgent] x86/cpu/intel: Add missing TLB cpuid values Git-Commit-ID: b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a Gitweb: https://git.kernel.org/tip/b837913fc2d9061bf9b8c0dd6bf2d24e2f98b84a Author: jacek.tomaka@poczta.fm AuthorDate: Tue, 24 Apr 2018 00:14:25 +0800 Committer: Thomas Gleixner CommitDate: Thu, 26 Apr 2018 21:42:44 +0200 x86/cpu/intel: Add missing TLB cpuid values Make kernel print the correct number of TLB entries on Intel Xeon Phi 7210 (and others) Before: [ 0.320005] Last level dTLB entries: 4KB 0, 2MB 0, 4MB 0, 1GB 0 After: [ 0.320005] Last level dTLB entries: 4KB 256, 2MB 128, 4MB 128, 1GB 16 The entries do exist in the official Intel SMD but the type column there is incorrect (states "Cache" where it should read "TLB"), but the entries for the values 0x6B, 0x6C and 0x6D are correctly described as 'Data TLB'. Signed-off-by: Jacek Tomaka Signed-off-by: Thomas Gleixner Link: https://lkml.kernel.org/r/20180423161425.24366-1-jacekt@dugeo.com --- arch/x86/kernel/cpu/intel.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index b9693b80fc21..60d1897041da 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -835,6 +835,9 @@ static const struct _tlb_table intel_tlb_table[] = { { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" }, { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" }, { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" }, + { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" }, + { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" }, + { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" }, { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" }, { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" }, { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },