From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752517AbbKAK3y (ORCPT ); Sun, 1 Nov 2015 05:29:54 -0500 Received: from terminus.zytor.com ([198.137.202.10]:45272 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752344AbbKAK3E (ORCPT ); Sun, 1 Nov 2015 05:29:04 -0500 Date: Sun, 1 Nov 2015 02:27:50 -0800 From: tip-bot for Aravind Gopalakrishnan Message-ID: Cc: ashok.raj@intel.com, bp@suse.de, peterz@infradead.org, Aravind.Gopalakrishnan@amd.com, linux-kernel@vger.kernel.org, tony.luck@intel.com, torvalds@linux-foundation.org, linux-edac@vger.kernel.org, hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, bp@alien8.de Reply-To: ashok.raj@intel.com, bp@alien8.de, hpa@zytor.com, mingo@kernel.org, tglx@linutronix.de, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Aravind.Gopalakrishnan@amd.com, tony.luck@intel.com, torvalds@linux-foundation.org, peterz@infradead.org, bp@suse.de In-Reply-To: <1446207099-24948-2-git-send-email-bp@alien8.de> References: <1446207099-24948-2-git-send-email-bp@alien8.de> To: linux-tip-commits@vger.kernel.org Subject: [tip:ras/core] x86/mce: Add a Scalable MCA vendor flags bit Git-Commit-ID: c7f54d21fb02e90042e6233b46716dcb244e70e6 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: c7f54d21fb02e90042e6233b46716dcb244e70e6 Gitweb: http://git.kernel.org/tip/c7f54d21fb02e90042e6233b46716dcb244e70e6 Author: Aravind Gopalakrishnan AuthorDate: Fri, 30 Oct 2015 13:11:37 +0100 Committer: Ingo Molnar CommitDate: Sun, 1 Nov 2015 11:26:13 +0100 x86/mce: Add a Scalable MCA vendor flags bit Scalable MCA (SMCA) is a new feature in AMD Fam17h processors which indicates presence of MCA extensions. MCA extensions expands existing register space for the MCE banks and also introduces a new MSR range to accommodate new banks. Add the detection bit. Signed-off-by: Aravind Gopalakrishnan [ Reformat mce_vendor_flags definitions and save indentation levels. Improve comments. ] Signed-off-by: Borislav Petkov Cc: Ashok Raj Cc: Borislav Petkov Cc: H. Peter Anvin Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Cc: Tony Luck Cc: linux-edac Link: http://lkml.kernel.org/r/1446207099-24948-2-git-send-email-bp@alien8.de Signed-off-by: Ingo Molnar --- arch/x86/include/asm/mce.h | 34 +++++++++++++++++++++------------- arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ 2 files changed, 23 insertions(+), 13 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 2dbc0bf..2ea4527 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -123,19 +123,27 @@ struct mca_config { }; struct mce_vendor_flags { - /* - * overflow recovery cpuid bit indicates that overflow - * conditions are not fatal - */ - __u64 overflow_recov : 1, - - /* - * SUCCOR stands for S/W UnCorrectable error COntainment - * and Recovery. It indicates support for data poisoning - * in HW and deferred error interrupts. - */ - succor : 1, - __reserved_0 : 62; + /* + * Indicates that overflow conditions are not fatal, when set. + */ + __u64 overflow_recov : 1, + + /* + * (AMD) SUCCOR stands for S/W UnCorrectable error COntainment and + * Recovery. It indicates support for data poisoning in HW and deferred + * error interrupts. + */ + succor : 1, + + /* + * (AMD) SMCA: This bit indicates support for Scalable MCA which expands + * the register space for each MCA bank and also increases number of + * banks. Also, to accommodate the new banks and registers, the MCA + * register space is moved to a new MSR range. + */ + smca : 1, + + __reserved_0 : 61; }; extern struct mce_vendor_flags mce_flags; diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c index 17b5ec6..3d631c4 100644 --- a/arch/x86/kernel/cpu/mcheck/mce.c +++ b/arch/x86/kernel/cpu/mcheck/mce.c @@ -1605,6 +1605,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) mce_amd_feature_init(c); mce_flags.overflow_recov = !!(ebx & BIT(0)); mce_flags.succor = !!(ebx & BIT(1)); + mce_flags.smca = !!(ebx & BIT(3)); + break; }