From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752851AbdLFQoA (ORCPT ); Wed, 6 Dec 2017 11:44:00 -0500 Received: from terminus.zytor.com ([65.50.211.136]:42045 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751941AbdLFQnx (ORCPT ); Wed, 6 Dec 2017 11:43:53 -0500 Date: Wed, 6 Dec 2017 08:39:55 -0800 From: tip-bot for Ganapatrao Kulkarni Message-ID: Cc: ganapatrao.kulkarni@cavium.com, catalin.marinas@arm.com, gklkml16@gmail.com, jonathan.cameron@huawei.com, mingo@kernel.org, robert.richter@cavium.com, will.deacon@arm.com, tglx@linutronix.de, jnair@caviumnetworks.com, zhangshaokun@hisilicon.com, mark.rutland@arm.com, hpa@zytor.com, peterz@infradead.org, linux-kernel@vger.kernel.org, alexander.shishkin@linux.intel.com, acme@redhat.com Reply-To: mingo@kernel.org, catalin.marinas@arm.com, gklkml16@gmail.com, jonathan.cameron@huawei.com, ganapatrao.kulkarni@cavium.com, zhangshaokun@hisilicon.com, will.deacon@arm.com, jnair@caviumnetworks.com, tglx@linutronix.de, robert.richter@cavium.com, hpa@zytor.com, mark.rutland@arm.com, acme@redhat.com, alexander.shishkin@linux.intel.com, linux-kernel@vger.kernel.org, peterz@infradead.org In-Reply-To: <20171016183222.25750-5-ganapatrao.kulkarni@cavium.com> References: <20171016183222.25750-5-ganapatrao.kulkarni@cavium.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf vendor events arm64: Add ThunderX2 implementation defined pmu core events Git-Commit-ID: d3964221ea14690fe51cb57331b88b5c69e4d2cb X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: d3964221ea14690fe51cb57331b88b5c69e4d2cb Gitweb: https://git.kernel.org/tip/d3964221ea14690fe51cb57331b88b5c69e4d2cb Author: Ganapatrao Kulkarni AuthorDate: Tue, 17 Oct 2017 00:02:21 +0530 Committer: Arnaldo Carvalho de Melo CommitDate: Tue, 5 Dec 2017 15:43:51 -0300 perf vendor events arm64: Add ThunderX2 implementation defined pmu core events This is not a full event list, but a short list of useful events. Signed-off-by: Ganapatrao Kulkarni Acked-by: Will Deacon Cc: Alexander Shishkin Cc: Catalin Marinas Cc: Ganapatrao Kulkarni Cc: Jayachandran C Cc: Jonathan Cameron Cc: Mark Rutland Cc: Peter Zijlstra Cc: Robert Richter Cc: Shaokun Zhang Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/20171016183222.25750-5-ganapatrao.kulkarni@cavium.com Signed-off-by: Arnaldo Carvalho de Melo --- .../arch/arm64/cavium/thunderx2-imp-def.json | 62 ++++++++++++++++++++++ tools/perf/pmu-events/arch/arm64/mapfile.csv | 15 ++++++ 2 files changed, 77 insertions(+) diff --git a/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json new file mode 100644 index 0000000..2db45c4 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/cavium/thunderx2-imp-def.json @@ -0,0 +1,62 @@ +[ + { + "PublicDescription": "Attributable Level 1 data cache access, read", + "EventCode": "0x40", + "EventName": "l1d_cache_rd", + "BriefDescription": "L1D cache read", + }, + { + "PublicDescription": "Attributable Level 1 data cache access, write ", + "EventCode": "0x41", + "EventName": "l1d_cache_wr", + "BriefDescription": "L1D cache write", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, read", + "EventCode": "0x42", + "EventName": "l1d_cache_refill_rd", + "BriefDescription": "L1D cache refill read", + }, + { + "PublicDescription": "Attributable Level 1 data cache refill, write", + "EventCode": "0x43", + "EventName": "l1d_cache_refill_wr", + "BriefDescription": "L1D refill write", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, read", + "EventCode": "0x4C", + "EventName": "l1d_tlb_refill_rd", + "BriefDescription": "L1D tlb refill read", + }, + { + "PublicDescription": "Attributable Level 1 data TLB refill, write", + "EventCode": "0x4D", + "EventName": "l1d_tlb_refill_wr", + "BriefDescription": "L1D tlb refill write", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, read", + "EventCode": "0x4E", + "EventName": "l1d_tlb_rd", + "BriefDescription": "L1D tlb read", + }, + { + "PublicDescription": "Attributable Level 1 data or unified TLB access, write", + "EventCode": "0x4F", + "EventName": "l1d_tlb_wr", + "BriefDescription": "L1D tlb write", + }, + { + "PublicDescription": "Bus access read", + "EventCode": "0x60", + "EventName": "bus_access_rd", + "BriefDescription": "Bus access read", + }, + { + "PublicDescription": "Bus access write", + "EventCode": "0x61", + "EventName": "bus_access_wr", + "BriefDescription": "Bus access write", + } +] diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv new file mode 100644 index 0000000..219d675 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv @@ -0,0 +1,15 @@ +# Format: +# MIDR,Version,JSON/file/pathname,Type +# +# where +# MIDR Processor version +# Variant[23:20] and Revision [3:0] should be zero. +# Version could be used to track version of of JSON file +# but currently unused. +# JSON/file/pathname is the path to JSON file, relative +# to tools/perf/pmu-events/arch/arm64/. +# Type is core, uncore etc +# +# +#Family-model,Version,Filename,EventType +0x00000000420f5160,v1,cavium,core