From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6A494C433F5 for ; Tue, 19 Apr 2022 17:50:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To:Date:Subject:Cc: To:From:Message-ID:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6CHn9k9gj6+8B4NVqesTE/SynKzGfCgJJqnJ3ckbZhk=; b=3jUgt28amUa3Gb sjCX7+OH0CtxTNJh0hh7Fg61iQ2qlzSumR9ms4F/WuhtdCCqfh/uFyb7oMvbOhvP5yZ63/CgTHV23 TSB3zylI67FDpeUTQKLmuI2Q542Xtmv+lu3+XebHtxGs4r5wmjiK5I0s16iIUl9L/YaTeTZOG7SGH vguHsywEmPl7HiDarvg0MRGJAAoUlD055e9bZoguR5+OIzQ34xQP21izEFz6LEqI6fBOjRf89Rt1D gTPi+dsO4kngcJvJh5eEawhnjL1vT91RTyYOC5v3ECVkmDTmuQCPnENRLAod5KLCcdmE9ZR4bmtUH 9fFQphjZhguv3j/LcOlA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngrzE-005SGR-HT; Tue, 19 Apr 2022 17:50:00 +0000 Received: from mout.gmx.net ([212.227.17.21]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ngryr-005S88-VW; Tue, 19 Apr 2022 17:49:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650390552; bh=MDs+/hTTaszs+7phQ7fP55iuGTCGnxSxNB+AmfhvHuI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=TnDZzT+t51BtIZ3ttWb8yCAiQ+bRXXd/u6G0viY+8w6Ni6c7lHcocNUuBZBnS4674 6WhQO0gk3GYZKK1EeXd9DNGPdu8vTbAeDU/gR+vtsnJYvfjdA+H3E5RicFlC3T2tAS /Cabuc5TQs7rUXlCugCortddBqGUNVZKFqbOjqCc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from [217.61.157.75] ([217.61.157.75]) by web-mail.gmx.net (3c-app-gmx-bap70.server.lan [172.19.172.170]) (via HTTP); Tue, 19 Apr 2022 19:49:12 +0200 MIME-Version: 1.0 Message-ID: From: Frank Wunderlich To: Krzysztof Kozlowski Cc: Frank Wunderlich , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Aw: Re: [RFC/RFT 1/6] dt-bindings: phy: rockchip: add pcie3 phy Date: Tue, 19 Apr 2022 19:49:12 +0200 Importance: normal Sensitivity: Normal In-Reply-To: <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> References: <20220416135458.104048-1-linux@fw-web.de> <20220416135458.104048-2-linux@fw-web.de> <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> X-UI-Message-Type: mail X-Priority: 3 X-Provags-ID: V03:K1:/NkW5UmqezUBTPZZjBz4iBJWrJkbhZBwHKWh0V8Jyr+1pKhoCegGDlCq58zKMqOdmW2O8 qFWG3xBwI/JlRCsgKDIK8CQBYs6tKtGZZsYo934557XRhtF/eLBlrxHGW+UzzHL29Pk168fbvTc/ OvR820AunbkK1yc3njh3Sx5eugb5TtM0ugLFARb7bmwQSMoEXbcDtNqwCs1HHLKMQGPDYWPxxyZl M74fV0GdY2s7Yh1BotHcRNi9nQgL9KwZxEVXJDSI7OKWmbxEcdT61wl+Hxv3VCTpwtjd+5o892Eg Sw= X-UI-Out-Filterresults: notjunk:1;V03:K0:aqAasQSxCdg=:Z5mk/vux6jXB0lRqbcp7Bk UJIJOWyt+bDd1jbTRt28lwBTb27anTGJNthdQC8F0KbTbeldXZ6uPBF1KXCOTiaQuMVtD1U+m hnQsLazT8r/MPjhmNW1sEOVKNNGDeRSSq1q6n94Hj5X0T3Csa9tBFfqn917kEsmJ0dz/X3MY6 Pk7zvjDiDkn0d1KXq2xsqFbUbHykddiuEnvxe1/GsZObmeUy+WdaC1NKl7zG06q0r2nQpLC8P u9MSbcKFFnUX7XsXmriHLY0xsYTPQozZgqgyfc5ZM4ouiuPS668cC5jyfkzWDZQtpyytMeceW O+p4bn8kIgBzNqZzwkvk8daiwSRkvgl9QvojKWeUYZcxLhnbNOICkSniTGG9xdzr7WphdwgQZ V6X22tRIkLgQzxrDi9Iji0l25j0z9ytR+sg4tgNwCjPn6IWljebWjcwrBdqYdCjhOJ6Nu5piy vfaOouiSJYlKk03KU7CFw8yhUqkElk3b7fK2RO1KhvihNkcrFZNejEnXXYFur8E4j1+D/MIr2 4q6UlSWznMyEYZXRW9crGkCR00/85yNxGSLaryFgsnn63K1WLWJMVlKmtPF009fPe6dh0NS5Z f1N2k1OWEkQEyfujdvkJziA6iq9oT5quw2EoIIqx/7GTUPZAQ8ZmBS9d6CsKpjTyht8IS7tbJ WIN9nu4KWK6d56emVSrxgdtX+kIf7x/3uqMqDlzyEpH5zjL9xHGNVd2cJPFm53xFHgXE/geLu A5GmJR47U9xPnXwLPTlmwG7rjN79csWKr502balpYnJSX6BGb94rekgHxR9cQRdj5h2VI3ahs kd7tLPH X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220419_104938_370765_F6A9B0EB X-CRM114-Status: GOOD ( 23.73 ) X-BeenThere: linux-rockchip@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Upstream kernel work for Rockchip platforms List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org > Gesendet: Montag, 18. April 2022 um 17:52 Uhr > Von: "Krzysztof Kozlowski" > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > new file mode 100644 > > index 000000000000..58a8ce175f13 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > Filename: vendor,hardware > so for example "rockchip,pcie3-phy" although Rob proposed recently for > other bindings using compatible as a base: > https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel.org/ ok, i rename > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/rockchip-pcie3-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip PCIe v3 phy > > + > > +maintainers: > > + - Heiko Stuebner > > + > > +properties: > > + compatible: > > + enum: > > + - rockchip,rk3568-pcie3-phy > > + - rockchip,rk3588-pcie3-phy > > + > > + reg: > > + maxItems: 2 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 3 > > + > > + clock-names: > > + contains: > > + anyOf: > > + - enum: [ refclk_m, refclk_n, pclk ] > > The list should be strictly ordered (defined), so: > items: > - const: ... > - const: ... > - const: ... > minItems: 1 > > However the question is - why the clocks have different amount? Is it > per different SoC implementation? i only know the rk3568, which needs the clocks defined here, don't know about rk3588 yet. in rk3568 TPM i have the pcie-part seems missing (at least the specific register definition), so i had used the driver as i got it from the downstream kernel. not yet looked if i find a rk3588 TPM and if this part is there as i cannot test it (one of the reasons this is a rfc/rft). > > + > > + "#phy-cells": > > + const: 0 > > + > > + resets: > > + maxItems: 1 > > + > > + reset-names: > > + const: phy > > + > > + rockchip,phy-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the phy "general register files" > > + > > + rockchip,pipe-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the pipe "general register files" > > + > > + rockchip,pcie30-phymode: > > + $ref: '/schemas/types.yaml#/definitions/uint32' > > + description: | > > + use PHY_MODE_PCIE_AGGREGATION if not defined > > I don't understand the description. Do you mean here a case when the > variable is missing? yes, if the property is not set, then value is PHY_MODE_PCIE_AGGREGATION = 4 > > + minimum: 0x0 > > + maximum: 0x4 > > Please explain these values. Register values should not be part of > bindings, but instead some logical behavior of hardware or its logic. it's a bitmask, so maybe description: | bit0: bifurcation for port 0 bit1: bifurcation for port 1 bit2: aggregation use PHY_MODE_PCIE_AGGREGATION (4) as default > > + > > + > > Just one blank line. > > > +required: > > + - compatible > > + - reg > > + - rockchip,phy-grf > > phy-cells as well > > > + > > +additionalProperties: false > > + > > +unevaluatedProperties: false > > Just one please, additionalProperties. ok > > + > > +examples: > > + - | > > + #include > > + pcie30phy: phy@fe8c0000 { > > + compatible = "rockchip,rk3568-pcie3-phy"; > > + reg = <0x0 0xfe8c0000 0x0 0x20000>; > > + #phy-cells = <0>; > > + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, > > + <&cru PCLK_PCIE30PHY>; > > Align the entry with opening '<'. Usually the most readable is one clock > per line. ok > > + clock-names = "refclk_m", "refclk_n", "pclk"; > > + resets = <&cru SRST_PCIE30PHY>; > > + reset-names = "phy"; > > + rockchip,phy-grf = <&pcie30_phy_grf>; > > + }; regards Frank _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8184FC433EF for ; Tue, 19 Apr 2022 17:50:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To:Date:Subject:Cc: To:From:Message-ID:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 19 Apr 2022 19:49:12 +0200 MIME-Version: 1.0 Message-ID: From: Frank Wunderlich To: Krzysztof Kozlowski Cc: Frank Wunderlich , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Aw: Re: [RFC/RFT 1/6] dt-bindings: phy: rockchip: add pcie3 phy Date: Tue, 19 Apr 2022 19:49:12 +0200 Importance: normal Sensitivity: Normal In-Reply-To: <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> References: <20220416135458.104048-1-linux@fw-web.de> <20220416135458.104048-2-linux@fw-web.de> <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> X-UI-Message-Type: mail X-Priority: 3 X-Provags-ID: V03:K1:/NkW5UmqezUBTPZZjBz4iBJWrJkbhZBwHKWh0V8Jyr+1pKhoCegGDlCq58zKMqOdmW2O8 qFWG3xBwI/JlRCsgKDIK8CQBYs6tKtGZZsYo934557XRhtF/eLBlrxHGW+UzzHL29Pk168fbvTc/ OvR820AunbkK1yc3njh3Sx5eugb5TtM0ugLFARb7bmwQSMoEXbcDtNqwCs1HHLKMQGPDYWPxxyZl M74fV0GdY2s7Yh1BotHcRNi9nQgL9KwZxEVXJDSI7OKWmbxEcdT61wl+Hxv3VCTpwtjd+5o892Eg Sw= X-UI-Out-Filterresults: notjunk:1;V03:K0:aqAasQSxCdg=:Z5mk/vux6jXB0lRqbcp7Bk UJIJOWyt+bDd1jbTRt28lwBTb27anTGJNthdQC8F0KbTbeldXZ6uPBF1KXCOTiaQuMVtD1U+m hnQsLazT8r/MPjhmNW1sEOVKNNGDeRSSq1q6n94Hj5X0T3Csa9tBFfqn917kEsmJ0dz/X3MY6 Pk7zvjDiDkn0d1KXq2xsqFbUbHykddiuEnvxe1/GsZObmeUy+WdaC1NKl7zG06q0r2nQpLC8P u9MSbcKFFnUX7XsXmriHLY0xsYTPQozZgqgyfc5ZM4ouiuPS668cC5jyfkzWDZQtpyytMeceW O+p4bn8kIgBzNqZzwkvk8daiwSRkvgl9QvojKWeUYZcxLhnbNOICkSniTGG9xdzr7WphdwgQZ V6X22tRIkLgQzxrDi9Iji0l25j0z9ytR+sg4tgNwCjPn6IWljebWjcwrBdqYdCjhOJ6Nu5piy vfaOouiSJYlKk03KU7CFw8yhUqkElk3b7fK2RO1KhvihNkcrFZNejEnXXYFur8E4j1+D/MIr2 4q6UlSWznMyEYZXRW9crGkCR00/85yNxGSLaryFgsnn63K1WLWJMVlKmtPF009fPe6dh0NS5Z f1N2k1OWEkQEyfujdvkJziA6iq9oT5quw2EoIIqx/7GTUPZAQ8ZmBS9d6CsKpjTyht8IS7tbJ WIN9nu4KWK6d56emVSrxgdtX+kIf7x/3uqMqDlzyEpH5zjL9xHGNVd2cJPFm53xFHgXE/geLu A5GmJR47U9xPnXwLPTlmwG7rjN79csWKr502balpYnJSX6BGb94rekgHxR9cQRdj5h2VI3ahs kd7tLPH X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220419_104938_370765_F6A9B0EB X-CRM114-Status: GOOD ( 23.73 ) X-BeenThere: linux-phy@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: Linux Phy Mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-phy" Errors-To: linux-phy-bounces+linux-phy=archiver.kernel.org@lists.infradead.org > Gesendet: Montag, 18. April 2022 um 17:52 Uhr > Von: "Krzysztof Kozlowski" > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > new file mode 100644 > > index 000000000000..58a8ce175f13 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > Filename: vendor,hardware > so for example "rockchip,pcie3-phy" although Rob proposed recently for > other bindings using compatible as a base: > https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel.org/ ok, i rename > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/rockchip-pcie3-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip PCIe v3 phy > > + > > +maintainers: > > + - Heiko Stuebner > > + > > +properties: > > + compatible: > > + enum: > > + - rockchip,rk3568-pcie3-phy > > + - rockchip,rk3588-pcie3-phy > > + > > + reg: > > + maxItems: 2 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 3 > > + > > + clock-names: > > + contains: > > + anyOf: > > + - enum: [ refclk_m, refclk_n, pclk ] > > The list should be strictly ordered (defined), so: > items: > - const: ... > - const: ... > - const: ... > minItems: 1 > > However the question is - why the clocks have different amount? Is it > per different SoC implementation? i only know the rk3568, which needs the clocks defined here, don't know about rk3588 yet. in rk3568 TPM i have the pcie-part seems missing (at least the specific register definition), so i had used the driver as i got it from the downstream kernel. not yet looked if i find a rk3588 TPM and if this part is there as i cannot test it (one of the reasons this is a rfc/rft). > > + > > + "#phy-cells": > > + const: 0 > > + > > + resets: > > + maxItems: 1 > > + > > + reset-names: > > + const: phy > > + > > + rockchip,phy-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the phy "general register files" > > + > > + rockchip,pipe-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the pipe "general register files" > > + > > + rockchip,pcie30-phymode: > > + $ref: '/schemas/types.yaml#/definitions/uint32' > > + description: | > > + use PHY_MODE_PCIE_AGGREGATION if not defined > > I don't understand the description. Do you mean here a case when the > variable is missing? yes, if the property is not set, then value is PHY_MODE_PCIE_AGGREGATION = 4 > > + minimum: 0x0 > > + maximum: 0x4 > > Please explain these values. Register values should not be part of > bindings, but instead some logical behavior of hardware or its logic. it's a bitmask, so maybe description: | bit0: bifurcation for port 0 bit1: bifurcation for port 1 bit2: aggregation use PHY_MODE_PCIE_AGGREGATION (4) as default > > + > > + > > Just one blank line. > > > +required: > > + - compatible > > + - reg > > + - rockchip,phy-grf > > phy-cells as well > > > + > > +additionalProperties: false > > + > > +unevaluatedProperties: false > > Just one please, additionalProperties. ok > > + > > +examples: > > + - | > > + #include > > + pcie30phy: phy@fe8c0000 { > > + compatible = "rockchip,rk3568-pcie3-phy"; > > + reg = <0x0 0xfe8c0000 0x0 0x20000>; > > + #phy-cells = <0>; > > + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, > > + <&cru PCLK_PCIE30PHY>; > > Align the entry with opening '<'. Usually the most readable is one clock > per line. ok > > + clock-names = "refclk_m", "refclk_n", "pclk"; > > + resets = <&cru SRST_PCIE30PHY>; > > + reset-names = "phy"; > > + rockchip,phy-grf = <&pcie30_phy_grf>; > > + }; regards Frank -- linux-phy mailing list linux-phy@lists.infradead.org https://lists.infradead.org/mailman/listinfo/linux-phy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 75827C4332F for ; Tue, 19 Apr 2022 17:50:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232215AbiDSRws (ORCPT ); Tue, 19 Apr 2022 13:52:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1356089AbiDSRwa (ORCPT ); Tue, 19 Apr 2022 13:52:30 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.17.21]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 48E50D9; Tue, 19 Apr 2022 10:49:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1650390552; bh=MDs+/hTTaszs+7phQ7fP55iuGTCGnxSxNB+AmfhvHuI=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date:In-Reply-To:References; b=TnDZzT+t51BtIZ3ttWb8yCAiQ+bRXXd/u6G0viY+8w6Ni6c7lHcocNUuBZBnS4674 6WhQO0gk3GYZKK1EeXd9DNGPdu8vTbAeDU/gR+vtsnJYvfjdA+H3E5RicFlC3T2tAS /Cabuc5TQs7rUXlCugCortddBqGUNVZKFqbOjqCc= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from [217.61.157.75] ([217.61.157.75]) by web-mail.gmx.net (3c-app-gmx-bap70.server.lan [172.19.172.170]) (via HTTP); Tue, 19 Apr 2022 19:49:12 +0200 MIME-Version: 1.0 Message-ID: From: Frank Wunderlich To: Krzysztof Kozlowski Cc: Frank Wunderlich , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Aw: Re: [RFC/RFT 1/6] dt-bindings: phy: rockchip: add pcie3 phy Content-Type: text/plain; charset=UTF-8 Date: Tue, 19 Apr 2022 19:49:12 +0200 Importance: normal Sensitivity: Normal In-Reply-To: <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> References: <20220416135458.104048-1-linux@fw-web.de> <20220416135458.104048-2-linux@fw-web.de> <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> X-UI-Message-Type: mail X-Priority: 3 X-Provags-ID: V03:K1:/NkW5UmqezUBTPZZjBz4iBJWrJkbhZBwHKWh0V8Jyr+1pKhoCegGDlCq58zKMqOdmW2O8 qFWG3xBwI/JlRCsgKDIK8CQBYs6tKtGZZsYo934557XRhtF/eLBlrxHGW+UzzHL29Pk168fbvTc/ OvR820AunbkK1yc3njh3Sx5eugb5TtM0ugLFARb7bmwQSMoEXbcDtNqwCs1HHLKMQGPDYWPxxyZl M74fV0GdY2s7Yh1BotHcRNi9nQgL9KwZxEVXJDSI7OKWmbxEcdT61wl+Hxv3VCTpwtjd+5o892Eg Sw= X-UI-Out-Filterresults: notjunk:1;V03:K0:aqAasQSxCdg=:Z5mk/vux6jXB0lRqbcp7Bk UJIJOWyt+bDd1jbTRt28lwBTb27anTGJNthdQC8F0KbTbeldXZ6uPBF1KXCOTiaQuMVtD1U+m hnQsLazT8r/MPjhmNW1sEOVKNNGDeRSSq1q6n94Hj5X0T3Csa9tBFfqn917kEsmJ0dz/X3MY6 Pk7zvjDiDkn0d1KXq2xsqFbUbHykddiuEnvxe1/GsZObmeUy+WdaC1NKl7zG06q0r2nQpLC8P u9MSbcKFFnUX7XsXmriHLY0xsYTPQozZgqgyfc5ZM4ouiuPS668cC5jyfkzWDZQtpyytMeceW O+p4bn8kIgBzNqZzwkvk8daiwSRkvgl9QvojKWeUYZcxLhnbNOICkSniTGG9xdzr7WphdwgQZ V6X22tRIkLgQzxrDi9Iji0l25j0z9ytR+sg4tgNwCjPn6IWljebWjcwrBdqYdCjhOJ6Nu5piy vfaOouiSJYlKk03KU7CFw8yhUqkElk3b7fK2RO1KhvihNkcrFZNejEnXXYFur8E4j1+D/MIr2 4q6UlSWznMyEYZXRW9crGkCR00/85yNxGSLaryFgsnn63K1WLWJMVlKmtPF009fPe6dh0NS5Z f1N2k1OWEkQEyfujdvkJziA6iq9oT5quw2EoIIqx/7GTUPZAQ8ZmBS9d6CsKpjTyht8IS7tbJ WIN9nu4KWK6d56emVSrxgdtX+kIf7x/3uqMqDlzyEpH5zjL9xHGNVd2cJPFm53xFHgXE/geLu A5GmJR47U9xPnXwLPTlmwG7rjN79csWKr502balpYnJSX6BGb94rekgHxR9cQRdj5h2VI3ahs kd7tLPH Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Gesendet: Montag, 18. April 2022 um 17:52 Uhr > Von: "Krzysztof Kozlowski" > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.= yaml b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > new file mode 100644 > > index 000000000000..58a8ce175f13 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > Filename: vendor,hardware > so for example "rockchip,pcie3-phy" although Rob proposed recently for > other bindings using compatible as a base: > https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel= .org/ ok, i rename > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/rockchip-pcie3-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip PCIe v3 phy > > + > > +maintainers: > > + - Heiko Stuebner > > + > > +properties: > > + compatible: > > + enum: > > + - rockchip,rk3568-pcie3-phy > > + - rockchip,rk3588-pcie3-phy > > + > > + reg: > > + maxItems: 2 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 3 > > + > > + clock-names: > > + contains: > > + anyOf: > > + - enum: [ refclk_m, refclk_n, pclk ] > > The list should be strictly ordered (defined), so: > items: > - const: ... > - const: ... > - const: ... > minItems: 1 > > However the question is - why the clocks have different amount? Is it > per different SoC implementation? i only know the rk3568, which needs the clocks defined here, don't know ab= out rk3588 yet. in rk3568 TPM i have the pcie-part seems missing (at least the specific re= gister definition), so i had used the driver as i got it from the downstre= am kernel. not yet looked if i find a rk3588 TPM and if this part is there as i canno= t test it (one of the reasons this is a rfc/rft). > > + > > + "#phy-cells": > > + const: 0 > > + > > + resets: > > + maxItems: 1 > > + > > + reset-names: > > + const: phy > > + > > + rockchip,phy-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the phy "general regi= ster files" > > + > > + rockchip,pipe-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the pipe "general reg= ister files" > > + > > + rockchip,pcie30-phymode: > > + $ref: '/schemas/types.yaml#/definitions/uint32' > > + description: | > > + use PHY_MODE_PCIE_AGGREGATION if not defined > > I don't understand the description. Do you mean here a case when the > variable is missing? yes, if the property is not set, then value is PHY_MODE_PCIE_AGGREGATION = =3D 4 > > + minimum: 0x0 > > + maximum: 0x4 > > Please explain these values. Register values should not be part of > bindings, but instead some logical behavior of hardware or its logic. it's a bitmask, so maybe description: | bit0: bifurcation for port 0 bit1: bifurcation for port 1 bit2: aggregation use PHY_MODE_PCIE_AGGREGATION (4) as default > > + > > + > > Just one blank line. > > > +required: > > + - compatible > > + - reg > > + - rockchip,phy-grf > > phy-cells as well > > > + > > +additionalProperties: false > > + > > +unevaluatedProperties: false > > Just one please, additionalProperties. ok > > + > > +examples: > > + - | > > + #include > > + pcie30phy: phy@fe8c0000 { > > + compatible =3D "rockchip,rk3568-pcie3-phy"; > > + reg =3D <0x0 0xfe8c0000 0x0 0x20000>; > > + #phy-cells =3D <0>; > > + clocks =3D <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PH= Y_REF_N>, > > + <&cru PCLK_PCIE30PHY>; > > Align the entry with opening '<'. Usually the most readable is one clock > per line. ok > > + clock-names =3D "refclk_m", "refclk_n", "pclk"; > > + resets =3D <&cru SRST_PCIE30PHY>; > > + reset-names =3D "phy"; > > + rockchip,phy-grf =3D <&pcie30_phy_grf>; > > + }; regards Frank From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A62DEC433EF for ; Tue, 19 Apr 2022 17:51:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:References:In-Reply-To:Date:Subject:Cc: To:From:Message-ID:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 19 Apr 2022 19:49:12 +0200 MIME-Version: 1.0 Message-ID: From: Frank Wunderlich To: Krzysztof Kozlowski Cc: Frank Wunderlich , linux-rockchip@lists.infradead.org, Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Krzysztof Kozlowski , Heiko Stuebner , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Philipp Zabel , Johan Jonker , Peter Geis , Michael Riesch , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Aw: Re: [RFC/RFT 1/6] dt-bindings: phy: rockchip: add pcie3 phy Date: Tue, 19 Apr 2022 19:49:12 +0200 Importance: normal Sensitivity: Normal In-Reply-To: <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> References: <20220416135458.104048-1-linux@fw-web.de> <20220416135458.104048-2-linux@fw-web.de> <38e60bb2-123b-09cf-d6ef-3a07c6984108@linaro.org> X-UI-Message-Type: mail X-Priority: 3 X-Provags-ID: V03:K1:/NkW5UmqezUBTPZZjBz4iBJWrJkbhZBwHKWh0V8Jyr+1pKhoCegGDlCq58zKMqOdmW2O8 qFWG3xBwI/JlRCsgKDIK8CQBYs6tKtGZZsYo934557XRhtF/eLBlrxHGW+UzzHL29Pk168fbvTc/ OvR820AunbkK1yc3njh3Sx5eugb5TtM0ugLFARb7bmwQSMoEXbcDtNqwCs1HHLKMQGPDYWPxxyZl M74fV0GdY2s7Yh1BotHcRNi9nQgL9KwZxEVXJDSI7OKWmbxEcdT61wl+Hxv3VCTpwtjd+5o892Eg Sw= X-UI-Out-Filterresults: notjunk:1;V03:K0:aqAasQSxCdg=:Z5mk/vux6jXB0lRqbcp7Bk UJIJOWyt+bDd1jbTRt28lwBTb27anTGJNthdQC8F0KbTbeldXZ6uPBF1KXCOTiaQuMVtD1U+m hnQsLazT8r/MPjhmNW1sEOVKNNGDeRSSq1q6n94Hj5X0T3Csa9tBFfqn917kEsmJ0dz/X3MY6 Pk7zvjDiDkn0d1KXq2xsqFbUbHykddiuEnvxe1/GsZObmeUy+WdaC1NKl7zG06q0r2nQpLC8P u9MSbcKFFnUX7XsXmriHLY0xsYTPQozZgqgyfc5ZM4ouiuPS668cC5jyfkzWDZQtpyytMeceW O+p4bn8kIgBzNqZzwkvk8daiwSRkvgl9QvojKWeUYZcxLhnbNOICkSniTGG9xdzr7WphdwgQZ V6X22tRIkLgQzxrDi9Iji0l25j0z9ytR+sg4tgNwCjPn6IWljebWjcwrBdqYdCjhOJ6Nu5piy vfaOouiSJYlKk03KU7CFw8yhUqkElk3b7fK2RO1KhvihNkcrFZNejEnXXYFur8E4j1+D/MIr2 4q6UlSWznMyEYZXRW9crGkCR00/85yNxGSLaryFgsnn63K1WLWJMVlKmtPF009fPe6dh0NS5Z f1N2k1OWEkQEyfujdvkJziA6iq9oT5quw2EoIIqx/7GTUPZAQ8ZmBS9d6CsKpjTyht8IS7tbJ WIN9nu4KWK6d56emVSrxgdtX+kIf7x/3uqMqDlzyEpH5zjL9xHGNVd2cJPFm53xFHgXE/geLu A5GmJR47U9xPnXwLPTlmwG7rjN79csWKr502balpYnJSX6BGb94rekgHxR9cQRdj5h2VI3ahs kd7tLPH X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220419_104938_370765_F6A9B0EB X-CRM114-Status: GOOD ( 23.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > Gesendet: Montag, 18. April 2022 um 17:52 Uhr > Von: "Krzysztof Kozlowski" > > diff --git a/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > new file mode 100644 > > index 000000000000..58a8ce175f13 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/phy/rockchip-pcie3-phy.yaml > > Filename: vendor,hardware > so for example "rockchip,pcie3-phy" although Rob proposed recently for > other bindings using compatible as a base: > https://lore.kernel.org/linux-devicetree/YlhkwvGdcf4ozTzG@robh.at.kernel.org/ ok, i rename > > @@ -0,0 +1,77 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/phy/rockchip-pcie3-phy.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Rockchip PCIe v3 phy > > + > > +maintainers: > > + - Heiko Stuebner > > + > > +properties: > > + compatible: > > + enum: > > + - rockchip,rk3568-pcie3-phy > > + - rockchip,rk3588-pcie3-phy > > + > > + reg: > > + maxItems: 2 > > + > > + clocks: > > + minItems: 1 > > + maxItems: 3 > > + > > + clock-names: > > + contains: > > + anyOf: > > + - enum: [ refclk_m, refclk_n, pclk ] > > The list should be strictly ordered (defined), so: > items: > - const: ... > - const: ... > - const: ... > minItems: 1 > > However the question is - why the clocks have different amount? Is it > per different SoC implementation? i only know the rk3568, which needs the clocks defined here, don't know about rk3588 yet. in rk3568 TPM i have the pcie-part seems missing (at least the specific register definition), so i had used the driver as i got it from the downstream kernel. not yet looked if i find a rk3588 TPM and if this part is there as i cannot test it (one of the reasons this is a rfc/rft). > > + > > + "#phy-cells": > > + const: 0 > > + > > + resets: > > + maxItems: 1 > > + > > + reset-names: > > + const: phy > > + > > + rockchip,phy-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the phy "general register files" > > + > > + rockchip,pipe-grf: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: phandle to the syscon managing the pipe "general register files" > > + > > + rockchip,pcie30-phymode: > > + $ref: '/schemas/types.yaml#/definitions/uint32' > > + description: | > > + use PHY_MODE_PCIE_AGGREGATION if not defined > > I don't understand the description. Do you mean here a case when the > variable is missing? yes, if the property is not set, then value is PHY_MODE_PCIE_AGGREGATION = 4 > > + minimum: 0x0 > > + maximum: 0x4 > > Please explain these values. Register values should not be part of > bindings, but instead some logical behavior of hardware or its logic. it's a bitmask, so maybe description: | bit0: bifurcation for port 0 bit1: bifurcation for port 1 bit2: aggregation use PHY_MODE_PCIE_AGGREGATION (4) as default > > + > > + > > Just one blank line. > > > +required: > > + - compatible > > + - reg > > + - rockchip,phy-grf > > phy-cells as well > > > + > > +additionalProperties: false > > + > > +unevaluatedProperties: false > > Just one please, additionalProperties. ok > > + > > +examples: > > + - | > > + #include > > + pcie30phy: phy@fe8c0000 { > > + compatible = "rockchip,rk3568-pcie3-phy"; > > + reg = <0x0 0xfe8c0000 0x0 0x20000>; > > + #phy-cells = <0>; > > + clocks = <&pmucru CLK_PCIE30PHY_REF_M>, <&pmucru CLK_PCIE30PHY_REF_N>, > > + <&cru PCLK_PCIE30PHY>; > > Align the entry with opening '<'. Usually the most readable is one clock > per line. ok > > + clock-names = "refclk_m", "refclk_n", "pclk"; > > + resets = <&cru SRST_PCIE30PHY>; > > + reset-names = "phy"; > > + rockchip,phy-grf = <&pcie30_phy_grf>; > > + }; regards Frank _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel