From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAC68C4CED1 for ; Sat, 5 Oct 2019 05:51:38 +0000 (UTC) Received: from alsa0.perex.cz (alsa0.perex.cz [77.48.224.243]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E9D99222C0 for ; Sat, 5 Oct 2019 05:51:37 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=alsa-project.org header.i=@alsa-project.org header.b="jOAg5xQQ" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E9D99222C0 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=alsa-devel-bounces@alsa-project.org Received: from alsa1.perex.cz (alsa1.perex.cz [207.180.221.201]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by alsa0.perex.cz (Postfix) with ESMTPS id BC6291674; Sat, 5 Oct 2019 07:50:45 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa0.perex.cz BC6291674 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=alsa-project.org; s=default; t=1570254695; bh=j1AfDjfo+5x/XDBQD5sFJZC48kBU5m66UoPOH/2oSXE=; h=From:To:Date:In-Reply-To:References:Cc:Subject:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=jOAg5xQQUVg5YjEZ+uRGD12LTFKT4OFFCEq3cV0VU/AgJaOgx0gJ5nRKQnCM7zWsr wznw2XHrGzKY7o5HnQsMSCN4+Olo8hGuvhcAPOWBgY7iTAWmGq5RPVo4l/uZt/Wkok QzEy73lmEtlUOAQGPLS9RE9V0Bf/2yQt+NaovX1Q= Received: from alsa1.perex.cz (localhost.localdomain [127.0.0.1]) by alsa1.perex.cz (Postfix) with ESMTP id 46F93F804FF; Sat, 5 Oct 2019 07:50:45 +0200 (CEST) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 49FC4F80506; Sat, 5 Oct 2019 07:50:43 +0200 (CEST) Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by alsa1.perex.cz (Postfix) with ESMTP id 07F19F800D2 for ; Sat, 5 Oct 2019 07:50:35 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 07F19F800D2 X-UUID: 35c438e7655b461588936e992b5e7918-20191005 X-UUID: 35c438e7655b461588936e992b5e7918-20191005 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 343177237; Sat, 05 Oct 2019 13:50:29 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sat, 5 Oct 2019 13:50:26 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sat, 5 Oct 2019 13:50:26 +0800 Message-ID: <1570254627.29077.15.camel@mtksdaap41> From: Yingjoe Chen To: Jiaxin Yu Date: Sat, 5 Oct 2019 13:50:27 +0800 In-Reply-To: <1569580317-21181-3-git-send-email-jiaxin.yu@mediatek.com> References: <1569580317-21181-1-git-send-email-jiaxin.yu@mediatek.com> <1569580317-21181-3-git-send-email-jiaxin.yu@mediatek.com> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-MTK: N Cc: mark.rutland@arm.com, alsa-devel@alsa-project.org, yong.liang@mediatek.com, robh+dt@kernel.org, lgirdwood@gmail.com, tzungbi@google.com, broonie@kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, eason.yen@mediatek.com, wim@linux-watchdog.org, linux@roeck-us.net Subject: Re: [alsa-devel] [PATCH v2 2/4] watchdog: mtk_wdt: mt8183: Add reset controller X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Fri, 2019-09-27 at 18:31 +0800, Jiaxin Yu wrote: > From: "yong.liang" > > Provide assert/deassert/reset API in watchdog driver. > Register reset controller for toprgu device in watchdog probe. I think we could improve this commit message so it is easier to understand what is provided by this patch. You could add something like this: Besides watchdog, MTK toprgu module also provide sub-system (eg, audio, camera, codec and connectivity) software reset functionality. > > Signed-off-by: yong.liang > --- > drivers/watchdog/Kconfig | 1 + > drivers/watchdog/mtk_wdt.c | 110 ++++++++++++++++++++++++++++++++++++- > 2 files changed, 110 insertions(+), 1 deletion(-) > > diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig > index 2e07caab9db2..629249fe5305 100644 > --- a/drivers/watchdog/Kconfig > +++ b/drivers/watchdog/Kconfig > @@ -717,6 +717,7 @@ config MEDIATEK_WATCHDOG > tristate "Mediatek SoCs watchdog support" > depends on ARCH_MEDIATEK || COMPILE_TEST > select WATCHDOG_CORE > + select RESET_CONTROLLER > help > Say Y here to include support for the watchdog timer > in Mediatek SoCs. > diff --git a/drivers/watchdog/mtk_wdt.c b/drivers/watchdog/mtk_wdt.c > index 9c3d0033260d..660fb0e48d8e 100644 > --- a/drivers/watchdog/mtk_wdt.c > +++ b/drivers/watchdog/mtk_wdt.c > @@ -20,6 +20,10 @@ > #include > #include > #include > +#include > +#include > +#include > +#include sorting please. > > #define WDT_MAX_TIMEOUT 31 > #define WDT_MIN_TIMEOUT 1 > @@ -44,17 +48,113 @@ > #define WDT_SWRST 0x14 > #define WDT_SWRST_KEY 0x1209 > > +#define WDT_SWSYSRST 0x18U > +#define WDT_SWSYS_RST_KEY 0x88000000 > + > #define DRV_NAME "mtk-wdt" > #define DRV_VERSION "1.0" > > static bool nowayout = WATCHDOG_NOWAYOUT; > static unsigned int timeout; > > +struct toprgu_reset { > + spinlock_t lock; /* Protects reset_controller access */ > + void __iomem *toprgu_swrst_base; > + int regofs; > + struct reset_controller_dev rcdev; > +}; I'm not sure we need a separate struct, especially when you need to duplicate wdt_base into this struct. After removing regofs/swrst_base, this struct only contain 2 members. Maybe you should just merge this into mtk_wdt_dev. > + > struct mtk_wdt_dev { > struct watchdog_device wdt_dev; > void __iomem *wdt_base; > + struct toprgu_reset reset_controller; > + const struct mtk_wdt_compatible *dev_comp; > +}; > + > +struct mtk_wdt_compatible { > + int sw_rst_num; > +}; > + > +static int toprgu_reset_assert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct toprgu_reset *data = container_of(rcdev, > + struct toprgu_reset, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = __raw_readl(data->toprgu_swrst_base + data->regofs); > + tmp |= BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->toprgu_swrst_base + data->regofs); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset_deassert(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + unsigned int tmp; > + unsigned long flags; > + struct toprgu_reset *data = container_of(rcdev, > + struct toprgu_reset, rcdev); > + > + spin_lock_irqsave(&data->lock, flags); > + > + tmp = __raw_readl(data->toprgu_swrst_base + data->regofs); > + tmp &= ~BIT(id); > + tmp |= WDT_SWSYS_RST_KEY; > + writel(tmp, data->toprgu_swrst_base + data->regofs); > + > + spin_unlock_irqrestore(&data->lock, flags); > + > + return 0; > +} > + > +static int toprgu_reset(struct reset_controller_dev *rcdev, > + unsigned long id) > +{ > + int ret; > + > + ret = toprgu_reset_assert(rcdev, id); > + if (ret) > + return ret; > + > + return toprgu_reset_deassert(rcdev, id); > +} > + > +static struct reset_control_ops toprgu_reset_ops = { static const > + .assert = toprgu_reset_assert, > + .deassert = toprgu_reset_deassert, > + .reset = toprgu_reset, > }; > > +static void toprgu_register_reset_controller(struct platform_device *pdev, > + int regofs) > +{ > + int ret; > + struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev); > + > + spin_lock_init(&mtk_wdt->reset_controller.lock); > + > + mtk_wdt->dev_comp = of_device_get_match_data(&pdev->dev); > + mtk_wdt->reset_controller.toprgu_swrst_base = mtk_wdt->wdt_base; > + mtk_wdt->reset_controller.regofs = regofs; > + mtk_wdt->reset_controller.rcdev.owner = THIS_MODULE; > + mtk_wdt->reset_controller.rcdev.nr_resets = > + mtk_wdt->dev_comp->sw_rst_num; > + mtk_wdt->reset_controller.rcdev.ops = &toprgu_reset_ops; > + mtk_wdt->reset_controller.rcdev.of_node = pdev->dev.of_node; > + ret = reset_controller_register(&mtk_wdt->reset_controller.rcdev); > + if (ret != 0) > + dev_err(&pdev->dev, > + "couldn't register wdt reset controller: %d\n", ret); If this fail, you should return it and make mtk_wdt_probe also return fail. > +} > + > static int mtk_wdt_restart(struct watchdog_device *wdt_dev, > unsigned long action, void *data) > { > @@ -187,9 +287,12 @@ static int mtk_wdt_probe(struct platform_device *pdev) > if (unlikely(err)) > return err; > > - dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", > + dev_info(&pdev->dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n", > mtk_wdt->wdt_dev.timeout, nowayout); > > + mtk_wdt->dev_comp = of_device_get_match_data(&pdev->dev); > + if (mtk_wdt->dev_comp) > + toprgu_register_reset_controller(pdev, WDT_SWSYSRST); Is this register offset WDT_SWSYSRST identical in all chips? If it is, you should hardcode it in assert/deassert, just like how we access other watchdog registers. If not, you should put it in mtk_wdt_compatible. > return 0; > } > > @@ -217,7 +320,12 @@ static int mtk_wdt_resume(struct device *dev) > } > #endif > > +static const struct mtk_wdt_compatible mt8183_compat = { > + .sw_rst_num = 18, > +}; > + > static const struct of_device_id mtk_wdt_dt_ids[] = { > + { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_compat }, > { .compatible = "mediatek,mt6589-wdt" }, sorting please Joe.C > { /* sentinel */ } > }; _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/alsa-devel