On Thu, Feb 27, 2014 at 02:08:45AM +0000, Li.Xiubo@freescale.com wrote:

> > +static const struct regmap_config fsl_ssi_regconfig = {
> > +	.max_register = CCSR_SSI_SACCDIS,
> > +	.reg_bits = 32,
> > +	.val_bits = 32,
> > +	.reg_stride = 4,
> > +#ifdef PPC
> > +	.val_format_endian = REGMAP_ENDIAN_BIG,
> > +#endif

> Is this really needed for your PPC platforms?

> If so, I think this should depend on one specified platform, which
> the CPU is in LE mode while the SSI is in BE mode...

Since the entire series depends on this patch due to the fact that it
makes changes throughout the driver we need this resolving to make any
progress here.  Perhaps it makes sense to restructure the series so that
this is at the end rather than start of the series?