Hi Edward,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on tegra/for-next]
[also build test ERROR on v4.18-rc6 next-20180727]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jorge-Sanjuan/ASoC-Tegra30-TDM-support/20180728-163720
base:   https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: arm-multi_v7_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        GCC_VERSION=7.2.0 make.cross ARCH=arm 

Note: the linux-review/Jorge-Sanjuan/ASoC-Tegra30-TDM-support/20180728-163720 HEAD 14bbc96df0fa027f7bc057eb2da8181baff4e22c builds fine.
      It only hurts bisectibility.

All errors (new ones prefixed by >>):

   sound/soc/tegra/tegra30_i2s.c: In function 'tegra30_i2s_hw_params':
>> sound/soc/tegra/tegra30_i2s.c:155:3: error: 'audio_bits' undeclared (first use in this function); did you mean 'audit_names'?
      audio_bits = TEGRA30_AUDIOCIF_BITS_24;
      ^~~~~~~~~~
      audit_names
   sound/soc/tegra/tegra30_i2s.c:155:3: note: each undeclared identifier is reported only once for each function it appears in

vim +155 sound/soc/tegra/tegra30_i2s.c

   133	
   134	static int tegra30_i2s_hw_params(struct snd_pcm_substream *substream,
   135					 struct snd_pcm_hw_params *params,
   136					 struct snd_soc_dai *dai)
   137	{
   138		struct device *dev = dai->dev;
   139		struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
   140		unsigned int mask, val, reg;
   141		int ret, sample_size, srate, i2sclock, bitcnt;
   142		struct tegra30_ahub_cif_conf cif_conf;
   143	
   144		if (params_channels(params) != 2)
   145			return -EINVAL;
   146	
   147		mask = TEGRA30_I2S_CTRL_BIT_SIZE_MASK;
   148		switch (params_format(params)) {
   149		case SNDRV_PCM_FORMAT_S16_LE:
   150			val = TEGRA30_I2S_CTRL_BIT_SIZE_16;
   151			sample_size = 16;
   152			break;
   153		case SNDRV_PCM_FORMAT_S24_LE:
   154			val = TEGRA30_I2S_CTRL_BIT_SIZE_24;
 > 155			audio_bits = TEGRA30_AUDIOCIF_BITS_24;
   156			sample_size = 24;
   157			break;
   158		case SNDRV_PCM_FORMAT_S32_LE:
   159			val = TEGRA30_I2S_CTRL_BIT_SIZE_32;
   160			sample_size = 32;
   161			break;
   162		default:
   163			return -EINVAL;
   164		}
   165	
   166		regmap_update_bits(i2s->regmap, TEGRA30_I2S_CTRL, mask, val);
   167	
   168		srate = params_rate(params);
   169	
   170		/* Final "* 2" required by Tegra hardware */
   171		i2sclock = srate * params_channels(params) * sample_size * 2;
   172	
   173		bitcnt = (i2sclock / (2 * srate)) - 1;
   174		if (bitcnt < 0 || bitcnt > TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_MASK_US)
   175			return -EINVAL;
   176	
   177		ret = clk_set_rate(i2s->clk_i2s, i2sclock);
   178		if (ret) {
   179			dev_err(dev, "Can't set I2S clock rate: %d\n", ret);
   180			return ret;
   181		}
   182	
   183		val = bitcnt << TEGRA30_I2S_TIMING_CHANNEL_BIT_COUNT_SHIFT;
   184	
   185		if (i2sclock % (2 * srate))
   186			val |= TEGRA30_I2S_TIMING_NON_SYM_ENABLE;
   187	
   188		regmap_write(i2s->regmap, TEGRA30_I2S_TIMING, val);
   189	
   190		cif_conf.threshold = 0;
   191		cif_conf.audio_channels = 2;
   192		cif_conf.client_channels = 2;
   193		cif_conf.audio_bits = TEGRA30_AUDIOCIF_BITS_16;
   194		cif_conf.client_bits = TEGRA30_AUDIOCIF_BITS_16;
   195		cif_conf.expand = 0;
   196		cif_conf.stereo_conv = 0;
   197		cif_conf.replicate = 0;
   198		cif_conf.truncate = 0;
   199		cif_conf.mono_conv = 0;
   200	
   201		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
   202			cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_RX;
   203			reg = TEGRA30_I2S_CIF_RX_CTRL;
   204		} else {
   205			cif_conf.direction = TEGRA30_AUDIOCIF_DIRECTION_TX;
   206			reg = TEGRA30_I2S_CIF_TX_CTRL;
   207		}
   208	
   209		i2s->soc_data->set_audio_cif(i2s->regmap, reg, &cif_conf);
   210	
   211		val = (1 << TEGRA30_I2S_OFFSET_RX_DATA_OFFSET_SHIFT) |
   212		      (1 << TEGRA30_I2S_OFFSET_TX_DATA_OFFSET_SHIFT);
   213		regmap_write(i2s->regmap, TEGRA30_I2S_OFFSET, val);
   214	
   215		return 0;
   216	}
   217	

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