On Fri, Feb 14, 2020 at 03:53:33PM +0800, derek.fang@realtek.com wrote:

> +	parent_clk = clk_get_parent(hw->clk);
> +	if (!parent_clk)
> +		dev_warn(component->dev,
> +			"Parent mclk of wclk not acquired in driver. Please ensure mclk was provided as %d Hz.\n",
> +			CLK_PLL2_FIN);
> +
> +	if (parent_rate != CLK_PLL2_FIN)
> +		dev_warn(component->dev, "clk %s only support %d Hz input\n",
> +			clk_name, CLK_PLL2_FIN);
> +
> +	if (rate != CLK_48) {
> +		dev_warn(component->dev, "clk %s only support %d Hz output\n",
> +			clk_name, CLK_48);
> +		rate = CLK_48;
> +	}

Are these genuine restrictions of the hardware or is this just being
hard coded in the driver?