From: Maxime Ripard <maxime@cerno.tech>
To: "Clément Péron" <peron.clem@gmail.com>
Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org,
linux-kernel@vger.kernel.org,
Jernej Skrabec <jernej.skrabec@siol.net>,
Takashi Iwai <tiwai@suse.com>, Rob Herring <robh+dt@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Marcus Cooper <codekipper@gmail.com>,
Chen-Yu Tsai <wens@csie.org>, Mark Brown <broonie@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v3 3/7] ASoC: sun4i-i2s: Add support for H6 I2S
Date: Tue, 28 Apr 2020 10:13:21 +0200 [thread overview]
Message-ID: <20200428081321.ht3el26yqhsnyfm4@gilmour.lan> (raw)
In-Reply-To: <20200426104115.22630-4-peron.clem@gmail.com>
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Hi,
On Sun, Apr 26, 2020 at 12:41:11PM +0200, Clément Péron wrote:
> From: Jernej Skrabec <jernej.skrabec@siol.net>
>
> H6 I2S is very similar to that in H3, except it supports up to 16
> channels.
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Marcus Cooper <codekipper@gmail.com>
> Signed-off-by: Clément Péron <peron.clem@gmail.com>
> ---
> sound/soc/sunxi/sun4i-i2s.c | 227 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 227 insertions(+)
>
> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
> index 4198a5410bf9..a23c9f2a3f8c 100644
> --- a/sound/soc/sunxi/sun4i-i2s.c
> +++ b/sound/soc/sunxi/sun4i-i2s.c
> @@ -124,6 +124,21 @@
> #define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
> #define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
>
> +/* Defines required for sun50i-h6 support */
> +#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET_MASK GENMASK(21, 20)
> +#define SUN50I_H6_I2S_TX_CHAN_SEL_OFFSET(offset) ((offset) << 20)
> +#define SUN50I_H6_I2S_TX_CHAN_SEL_MASK GENMASK(19, 16)
> +#define SUN50I_H6_I2S_TX_CHAN_SEL(chan) ((chan - 1) << 16)
> +#define SUN50I_H6_I2S_TX_CHAN_EN_MASK GENMASK(15, 0)
> +#define SUN50I_H6_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1))
> +
> +#define SUN50I_H6_I2S_TX_CHAN_MAP0_REG 0x44
> +#define SUN50I_H6_I2S_TX_CHAN_MAP1_REG 0x48
> +
> +#define SUN50I_H6_I2S_RX_CHAN_SEL_REG 0x64
> +#define SUN50I_H6_I2S_RX_CHAN_MAP0_REG 0x68
> +#define SUN50I_H6_I2S_RX_CHAN_MAP1_REG 0x6C
> +
> struct sun4i_i2s;
>
> /**
> @@ -469,6 +484,65 @@ static int sun8i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
> return 0;
> }
>
> +static int sun50i_i2s_set_chan_cfg(const struct sun4i_i2s *i2s,
> + const struct snd_pcm_hw_params *params)
> +{
> + unsigned int channels = params_channels(params);
> + unsigned int slots = channels;
> + unsigned int lrck_period;
> +
> + if (i2s->slots)
> + slots = i2s->slots;
> +
> + /* Map the channels for playback and capture */
> + regmap_write(i2s->regmap, SUN50I_H6_I2S_TX_CHAN_MAP1_REG, 0x76543210);
> + regmap_write(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_MAP1_REG, 0x76543210);
> +
> + /* Configure the channels */
> + regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
> + SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
> + SUN50I_H6_I2S_TX_CHAN_SEL(channels));
> + regmap_update_bits(i2s->regmap, SUN50I_H6_I2S_RX_CHAN_SEL_REG,
> + SUN50I_H6_I2S_TX_CHAN_SEL_MASK,
> + SUN50I_H6_I2S_TX_CHAN_SEL(channels));
> +
> + regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
> + SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
> + SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
> + regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
> + SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
> + SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
> +
> + switch (i2s->format & SND_SOC_DAIFMT_FORMAT_MASK) {
> + case SND_SOC_DAIFMT_DSP_A:
> + case SND_SOC_DAIFMT_DSP_B:
> + case SND_SOC_DAIFMT_LEFT_J:
> + case SND_SOC_DAIFMT_RIGHT_J:
> + lrck_period = params_physical_width(params) * slots;
> + break;
> +
> + case SND_SOC_DAIFMT_I2S:
> + lrck_period = params_physical_width(params);
> + break;
> +
> + default:
> + return -EINVAL;
> + }
> +
> + if (i2s->slot_width)
> + lrck_period = i2s->slot_width;
> +
> + regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
> + SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
> + SUN8I_I2S_FMT0_LRCK_PERIOD(lrck_period));
> +
> + regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
> + SUN50I_H6_I2S_TX_CHAN_EN_MASK,
> + SUN50I_H6_I2S_TX_CHAN_EN(channels));
> +
> + return 0;
> +}
> +
> static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
> struct snd_pcm_hw_params *params,
> struct snd_soc_dai *dai)
> @@ -694,6 +768,108 @@ static int sun8i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
> return 0;
> }
>
> +static int sun50i_i2s_set_soc_fmt(const struct sun4i_i2s *i2s,
> + unsigned int fmt)
The alignment is off here
> +{
> + u32 mode, val;
> + u8 offset;
> +
> + /*
> + * DAI clock polarity
> + *
> + * The setup for LRCK contradicts the datasheet, but under a
> + * scope it's clear that the LRCK polarity is reversed
> + * compared to the expected polarity on the bus.
> + */
Did you check this or has it been copy-pasted?
Thanks!
Maxime
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next prev parent reply other threads:[~2020-04-28 8:14 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-26 10:41 [PATCH v3 0/7] Add H6 I2S support Clément Péron
2020-04-26 10:41 ` [PATCH v3 1/7] ASoC: sun4i-i2s: Adjust LRCLK width Clément Péron
2020-04-28 8:02 ` Maxime Ripard
2020-04-26 10:41 ` [PATCH v3 2/7] dt-bindings: ASoC: sun4i-i2s: Add H6 compatible Clément Péron
2020-04-28 8:08 ` Maxime Ripard
2020-05-11 22:26 ` Rob Herring
2020-04-26 10:41 ` [PATCH v3 3/7] ASoC: sun4i-i2s: Add support for H6 I2S Clément Péron
2020-04-28 8:13 ` Maxime Ripard [this message]
2020-04-28 8:55 ` Clément Péron
2020-04-29 12:35 ` Maxime Ripard
2020-04-29 16:33 ` Clément Péron
2020-04-30 8:46 ` Maxime Ripard
2020-04-30 14:00 ` Clément Péron
2020-05-04 12:09 ` Maxime Ripard
2020-05-04 19:43 ` Clément Péron
2020-07-29 14:39 ` Maxime Ripard
2020-07-29 15:15 ` Mark Brown
2020-09-03 20:02 ` Clément Péron
2020-09-03 20:58 ` Maxime Ripard
2020-09-04 2:54 ` Samuel Holland
[not found] ` <20200910143314.qku7po6htiiq5lzf@gilmour.lan>
2020-09-12 20:29 ` Samuel Holland
2020-09-17 13:21 ` Maxime Ripard
2020-09-17 13:55 ` Clément Péron
2020-09-17 14:06 ` Maxime Ripard
2020-09-20 12:38 ` Clément Péron
2020-04-26 10:41 ` [PATCH v3 4/7] ASoC: sun4i-i2s: Set sign extend sample Clément Péron
2020-04-26 10:41 ` [PATCH v3 5/7] ASoc: sun4i-i2s: Add 20 and 24 bit support Clément Péron
2020-04-26 10:41 ` [PATCH v3 6/7] ASoC: sun4i-i2s: Adjust regmap settings Clément Péron
2020-04-27 11:03 ` Chen-Yu Tsai
2020-05-03 11:42 ` Clément Péron
2020-04-26 10:41 ` [PATCH v3 7/7] arm64: dts: sun50i-h6: Add HDMI audio to H6 DTSI Clément Péron
2020-04-26 11:51 ` Clément Péron
2020-04-28 8:14 ` Maxime Ripard
2020-04-28 14:36 ` Clément Péron
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