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d="scan'208";a="336142762" Received: from smile.fi.intel.com (HELO smile) ([10.237.68.40]) by orsmga008.jf.intel.com with ESMTP; 16 Sep 2020 12:25:53 -0700 Received: from andy by smile with local (Exim 4.94) (envelope-from ) id 1kIcrF-00H9bG-4F; Wed, 16 Sep 2020 22:12:45 +0300 Date: Wed, 16 Sep 2020 22:12:45 +0300 From: Andy Shevchenko To: "Rojewski, Cezary" Subject: Re: [PATCH v5 01/13] ASoC: Intel: Add catpt device Message-ID: <20200916191245.GF3956970@smile.fi.intel.com> References: <20200915162944.16241-1-cezary.rojewski@intel.com> <20200915162944.16241-2-cezary.rojewski@intel.com> <20200916152455.GP3956970@smile.fi.intel.com> <20200916165614.GC3956970@smile.fi.intel.com> <9050ad4f60764a55a98579e494bd53f0@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9050ad4f60764a55a98579e494bd53f0@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Cc: "pierre-louis.bossart@linux.intel.com" , "alsa-devel@alsa-project.org" , "Kaczmarski, Filip" , "N, Harshapriya" , "Barlik, Marcin" , "zwisler@google.com" , "lgirdwood@gmail.com" , "tiwai@suse.com" , "Proborszcz, Filip" , "broonie@kernel.org" , "amadeuszx.slawinski@linux.intel.com" , "Wasko, Michal" , "cujomalainey@chromium.org" , "Hejmowski, Krzysztof" , "Papierkowski, Piotr \(Habana\)" , "Gopal, Vamshi Krishna" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Wed, Sep 16, 2020 at 06:30:27PM +0000, Rojewski, Cezary wrote: > > On Wed, Sep 16, 2020 at 06:24:56PM +0300, Andy Shevchenko wrote: > > > On Tue, Sep 15, 2020 at 06:29:32PM +0200, Cezary Rojewski wrote: > > > > Declare base structures, registers and device routines for the catpt > > > > solution. Catpt deprecates and is a direct replacement for > > > > sound/soc/intel/haswell. Supports Lynxpoint and Wildcat Point both. > > > > > > Few nit-picks below. Overall looks good, FWIW, > > > Reviewed-by: Andy Shevchenko > > > > Actually hold on. See below. > > > > > > +void catpt_sram_init(struct resource *sram, u32 start, u32 size); > > > > +void catpt_sram_free(struct resource *sram); > > > > +struct resource * > > > > +catpt_request_region(struct resource *root, resource_size_t size); > > > > These seems dangling declarations that has to be moved to the > > corresponding > > patch. Please, revisit entire series to be sure that: > > > > - each patch doesn't add any warnings on W=1 > > - each patch doesn't have dangling stuff > > - each patch is bisectable for compilation and run-time > > > > TLDR: you want patches: > 6/13 ASoC: Intel: catpt: PCM operations > 5/13 ASoC: Intel: catpt: Add IPC messages > 4/13 ASoC: Intel: catpt: Implement IPC protocol > 3/13 ASoC: Intel: catpt: Firmware loading and context restore > 2/13 ASoC: Intel: catpt: Define DSP operations > 1/13 ASoC: Intel: Add catpt device > > squashed. There is no other way to achieve that without combining > all the core-code together. fs and traces can be provided separately, > but not the first 6. No. My point is introduce header (declaration) with definition (c-file) together. Like those three of four functions. -- With Best Regards, Andy Shevchenko