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[213.245.241.245]) by smtp.gmail.com with ESMTPSA id d18sm5417473wrm.10.2020.10.03.07.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Oct 2020 07:20:08 -0700 (PDT) From: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= To: Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Brown , Liam Girdwood Subject: [PATCH v6 07/14] ASoC: sun4i-i2s: Fix setting of FIFO modes Date: Sat, 3 Oct 2020 16:19:43 +0200 Message-Id: <20201003141950.455829-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20201003141950.455829-1-peron.clem@gmail.com> References: <20201003141950.455829-1-peron.clem@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: devicetree@vger.kernel.org, Jernej Skrabec , alsa-devel@alsa-project.org, Samuel Holland , linux-kernel@vger.kernel.org, Takashi Iwai , Marcus Cooper , linux-sunxi@googlegroups.com, =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= , linux-arm-kernel@lists.infradead.org X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" From: Samuel Holland Because SUN4I_I2S_FIFO_CTRL_REG is volatile, writes done while the regmap is cache-only are ignored. To work around this, move the configuration to a callback that runs while the ASoC core has a runtime PM reference to the device. Signed-off-by: Samuel Holland Reviewed-by: Chen-Yu Tsai Signed-off-by: Clément Péron --- sound/soc/sunxi/sun4i-i2s.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c index 92671eb94db9..fef68146d648 100644 --- a/sound/soc/sunxi/sun4i-i2s.c +++ b/sound/soc/sunxi/sun4i-i2s.c @@ -588,6 +588,13 @@ static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream, return ret; } + /* Set significant bits in our FIFOs */ + regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, + SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | + SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, + SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | + SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); + switch (params_physical_width(params)) { case 16: width = DMA_SLAVE_BUSWIDTH_2_BYTES; @@ -916,13 +923,6 @@ static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) return ret; } - /* Set significant bits in our FIFOs */ - regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, - SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK | - SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK, - SUN4I_I2S_FIFO_CTRL_TX_MODE(1) | - SUN4I_I2S_FIFO_CTRL_RX_MODE(1)); - i2s->format = fmt; return 0; -- 2.25.1