From: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
To: alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org,
linuxppc-dev@lists.ozlabs.org
Cc: bkylerussell@gmail.com, ariel.dalessandro@collabora.com,
kuninori.morimoto.gx@renesas.com, Xiubo.Lee@gmail.com,
shengjiu.wang@gmail.com, tiwai@suse.com, lgirdwood@gmail.com,
nicoleotsuka@gmail.com, broonie@kernel.org,
michael@amarulasolutions.com, festevam@gmail.com
Subject: [RFC patch 3/5] ASoC: tlv320aic31xx: Add divs for bclk as clk_in
Date: Fri, 19 Nov 2021 12:32:46 -0300 [thread overview]
Message-ID: <20211119153248.419802-4-ariel.dalessandro@collabora.com> (raw)
In-Reply-To: <20211119153248.419802-1-ariel.dalessandro@collabora.com>
Add divisors for rates needed when the clk_in is set to BCLK.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
---
sound/soc/codecs/tlv320aic31xx.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/sound/soc/codecs/tlv320aic31xx.c b/sound/soc/codecs/tlv320aic31xx.c
index 1aec03d834d0..e8307f0737f2 100644
--- a/sound/soc/codecs/tlv320aic31xx.c
+++ b/sound/soc/codecs/tlv320aic31xx.c
@@ -195,46 +195,66 @@ struct aic31xx_rate_divs {
static const struct aic31xx_rate_divs aic31xx_divs[] = {
/* mclk/p rate pll: r j d dosr ndac mdac aors nadc madc */
/* 8k rate */
+ { 512000, 8000, 4, 48, 0, 128, 48, 2, 128, 48, 2},
{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
{12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
{12500000, 8000, 1, 7, 8643, 128, 48, 2, 128, 48, 2},
/* 11.025k rate */
+ { 705600, 11025, 3, 48, 0, 128, 24, 3, 128, 24, 3},
{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
{12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
{12500000, 11025, 1, 7, 2253, 128, 32, 2, 128, 32, 2},
/* 16k rate */
+ { 512000, 16000, 4, 48, 0, 128, 16, 3, 128, 16, 3},
+ { 1024000, 16000, 2, 48, 0, 128, 16, 3, 128, 16, 3},
{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
{12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
{12500000, 16000, 1, 7, 8643, 128, 24, 2, 128, 24, 2},
/* 22.05k rate */
+ { 705600, 22050, 4, 36, 0, 128, 12, 3, 128, 12, 3},
+ { 1411200, 22050, 2, 36, 0, 128, 12, 3, 128, 12, 3},
{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
{12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
{12500000, 22050, 1, 7, 2253, 128, 16, 2, 128, 16, 2},
/* 32k rate */
+ { 1024000, 32000, 2, 48, 0, 128, 12, 2, 128, 12, 2},
+ { 2048000, 32000, 1, 48, 0, 128, 12, 2, 128, 12, 2},
{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
{12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
{12500000, 32000, 1, 7, 8643, 128, 12, 2, 128, 12, 2},
/* 44.1k rate */
+ { 1411200, 44100, 2, 32, 0, 128, 8, 2, 128, 8, 2},
+ { 2822400, 44100, 1, 32, 0, 128, 8, 2, 128, 8, 2},
{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
{12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
{12500000, 44100, 1, 7, 2253, 128, 8, 2, 128, 8, 2},
/* 48k rate */
+ { 1536000, 48000, 2, 32, 0, 128, 8, 2, 128, 8, 2},
+ { 3072000, 48000, 1, 32, 0, 128, 8, 2, 128, 8, 2},
{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
{12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
{12500000, 48000, 1, 7, 8643, 128, 8, 2, 128, 8, 2},
/* 88.2k rate */
+ { 2822400, 88200, 2, 16, 0, 64, 8, 2, 64, 8, 2},
+ { 5644800, 88200, 1, 16, 0, 64, 8, 2, 64, 8, 2},
{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
{12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
{12500000, 88200, 1, 7, 2253, 64, 8, 2, 64, 8, 2},
/* 96k rate */
+ { 3072000, 96000, 2, 16, 0, 64, 8, 2, 64, 8, 2},
+ { 6144000, 96000, 1, 16, 0, 64, 8, 2, 64, 8, 2},
{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
{12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
{12500000, 96000, 1, 7, 8643, 64, 8, 2, 64, 8, 2},
/* 176.4k rate */
+ { 5644800, 176400, 2, 8, 0, 32, 8, 2, 32, 8, 2},
+ {11289600, 176400, 1, 8, 0, 32, 8, 2, 32, 8, 2},
{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
{12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
{12500000, 176400, 1, 7, 2253, 32, 8, 2, 32, 8, 2},
/* 192k rate */
+ { 6144000, 192000, 2, 8, 0, 32, 8, 2, 32, 8, 2},
+ {12288000, 192000, 1, 8, 0, 32, 8, 2, 32, 8, 2},
{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
{12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
{12500000, 192000, 1, 7, 8643, 32, 8, 2, 32, 8, 2},
--
2.30.2
next prev parent reply other threads:[~2021-11-22 7:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-19 15:32 [RFC patch 0/5] Support BCLK input clock in tlv320aic31xx Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 1/5] ASoC: tlv320aic31xx: Fix typo in BCLK clock name Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 2/5] ASoC: tlv320aic31xx: Add support for pll_r coefficient Ariel D'Alessandro
2021-11-22 14:22 ` Mark Brown
2021-11-22 14:24 ` Michael Nazzareno Trimarchi
2021-11-22 14:33 ` Mark Brown
2021-11-19 15:32 ` Ariel D'Alessandro [this message]
2021-11-19 15:32 ` [RFC patch 4/5] ASoC: tlv320aic31xx: Handle BCLK set as PLL input configuration Ariel D'Alessandro
2021-11-19 15:32 ` [RFC patch 5/5] ASoC: fsl-asoc-card: Support fsl, imx-audio-tlv320aic31xx codec Ariel D'Alessandro
2021-12-03 17:27 ` [RFC patch 5/5] ASoC: fsl-asoc-card: Support fsl,imx-audio-tlv320aic31xx codec Ariel D'Alessandro
2021-11-23 0:00 ` [RFC patch 0/5] Support BCLK input clock in tlv320aic31xx Mark Brown
2021-12-03 17:25 ` Ariel D'Alessandro
2021-12-03 17:34 ` Mark Brown
2021-12-03 17:37 ` Ariel D'Alessandro
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