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d="scan'208";a="286971482" Received: from jrwang2-mobl.amr.corp.intel.com (HELO [10.212.82.25]) ([10.212.82.25]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jul 2020 13:10:46 -0700 Subject: Re: [PATCH v2] ASoC: Intel: boards: eve: Fix DMIC records zero To: "N, Harshapriya" , "alsa-devel@alsa-project.org" , "broonie@kernel.org" References: <1596129988-304-1-git-send-email-harshapriya.n@intel.com> <2788f0fd-adaa-c56d-6801-503432ba7ee6@linux.intel.com> <8cd83872-c6d3-faf2-bd1a-963af90d7d2a@linux.intel.com> From: Pierre-Louis Bossart Message-ID: <4773a165-ac6d-36a0-2105-169e2d79a327@linux.intel.com> Date: Thu, 30 Jul 2020 15:10:45 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Cc: "Lu, Brent" , "Gopal, Vamshi Krishna" X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" >>>>> case SND_SOC_DAPM_POST_PMD: >>>>> - clk_disable_unprepare(priv->mclk); >>>>> - clk_disable_unprepare(priv->sclk); >>>>> + if (__clk_is_enabled(priv->mclk)) >>>>> + clk_disable_unprepare(priv->mclk); >>>>> + >>>> >>>> [1] this seems wrong in case you have two SSPs working, and stop one. >>>> This would turn off the mclk while one of the two SSPs is still working. >>> For this platform we use either headset or dmic. >>> There is no way we can record simultaneously using different devices. >>> So disabling mclk might not be harmful here. But this case will always be true >> too :). >> >> Maybe CRAS prevents you from recording on two inputs, but it looks like you >> have independent front-ends so in theory couldn't you record at the alsa hw: >> device level? Is this really mutually exclusive at the hardware level? > True. Its not mutually exclusive at hardware level. the following might be safe > if (!__clk_is_enabled(priv->sclk0)) && (!__clk_is_enabled(priv->sclk1)) > clk_disable_unprepare(priv->mclk); I don't understand DAPM well-enough to know if these independent platform clock control routines are serialized by design or if this could be racy?