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Mon, 25 Nov 2019 11:08:03 +0100 (CET) Received: by alsa1.perex.cz (Postfix, from userid 50401) id 0A379F8016F; Mon, 25 Nov 2019 11:08:02 +0100 (CET) Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [IPv6:2001:67c:670:201:290:27ff:fe1d:cc33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by alsa1.perex.cz (Postfix) with ESMTPS id 8462CF800AB for ; Mon, 25 Nov 2019 11:07:59 +0100 (CET) DKIM-Filter: OpenDKIM Filter v2.11.0 alsa1.perex.cz 8462CF800AB Received: from lupine.hi.pengutronix.de ([2001:67c:670:100:3ad5:47ff:feaf:1a17] helo=lupine) by metis.ext.pengutronix.de with esmtp (Exim 4.92) (envelope-from ) id 1iZBHG-00050V-8t; Mon, 25 Nov 2019 11:07:30 +0100 Message-ID: <49c94039ba327a1295fdfd5d74dca0b9805269b0.camel@pengutronix.de> From: Philipp Zabel To: Jiaxin Yu , broonie@kernel.org, mark.rutland@arm.com, yingjoe.chen@mediatek.com, robh+dt@kernel.org, linux@roeck-us.net, wim@linux-watchdog.org Date: Mon, 25 Nov 2019 11:07:25 +0100 In-Reply-To: <1574651030-29519-2-git-send-email-jiaxin.yu@mediatek.com> References: <1574651030-29519-1-git-send-email-jiaxin.yu@mediatek.com> <1574651030-29519-2-git-send-email-jiaxin.yu@mediatek.com> User-Agent: Evolution 3.30.5-1.1 MIME-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: alsa-devel@alsa-project.org Cc: alsa-devel@alsa-project.org, yong.liang@mediatek.com, lgirdwood@gmail.com, tzungbi@google.com, linux-mediatek@lists.infradead.org, eason.yen@mediatek.com, linux-arm-kernel@lists.infradead.org Subject: Re: [alsa-devel] [PATCH v5 1/2] dt-bindings: mediatek: mt8183: Add #reset-cells X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Mon, 2019-11-25 at 11:03 +0800, Jiaxin Yu wrote: > From: "yong.liang" > > Add #reset-cells property and update example > > Signed-off-by: yong.liang > Signed-off-by: jiaxin.yu > Reviewed-by: Yingjoe Chen > --- > .../devicetree/bindings/watchdog/mtk-wdt.txt | 10 ++++++--- > .../reset-controller/mt2712-resets.h | 22 +++++++++++++++++++ > .../reset-controller/mt8183-resets.h | 15 +++++++++++++ > 3 files changed, 44 insertions(+), 3 deletions(-) > create mode 100644 include/dt-bindings/reset-controller/mt2712-resets.h > > diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > index 3ee625d0812f..4dd36bd3f1ad 100644 > --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt > @@ -4,6 +4,7 @@ Required properties: > > - compatible should contain: > "mediatek,mt2701-wdt", "mediatek,mt6589-wdt": for MT2701 > + "mediatek,mt2712-wdt", "mediatek,mt6589-wdt": for MT2712 > "mediatek,mt6589-wdt": for MT6589 > "mediatek,mt6797-wdt", "mediatek,mt6589-wdt": for MT6797 > "mediatek,mt7622-wdt", "mediatek,mt6589-wdt": for MT7622 > @@ -16,11 +17,14 @@ Required properties: > > Optional properties: > - timeout-sec: contains the watchdog timeout in seconds. > +- #reset-cells: Should be 1. > > Example: > > -wdt: watchdog@10000000 { > - compatible = "mediatek,mt6589-wdt"; > - reg = <0x10000000 0x18>; > +watchdog: watchdog@10007000 { > + compatible = "mediatek,mt8183-wdt", > + "mediatek,mt6589-wdt"; > + reg = <0 0x10007000 0 0x100>; > timeout-sec = <10>; > + #reset-cells = <1>; > }; > diff --git a/include/dt-bindings/reset-controller/mt2712-resets.h b/include/dt-bindings/reset-controller/mt2712-resets.h > new file mode 100644 > index 000000000000..e81c8bb311b7 > --- /dev/null > +++ b/include/dt-bindings/reset-controller/mt2712-resets.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2019 MediaTek Inc. > + * Author: Yong Liang > + */ > + > +#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2712 > +#define _DT_BINDINGS_RESET_CONTROLLER_MT2712 > + > +#define MT2712_TOPRGU_INFRA_SW_RST 0 > +#define MT2712_TOPRGU_MM_SW_RST 1 > +#define MT2712_TOPRGU_MFG_SW_RST 2 > +#define MT2712_TOPRGU_VENC_SW_RST 3 > +#define MT2712_TOPRGU_VDEC_SW_RST 4 > +#define MT2712_TOPRGU_IMG_SW_RST 5 > +#define MT2712_TOPRGU_INFRA_AO_SW_RST 8 > +#define MT2712_TOPRGU_USB_SW_RST 9 > +#define MT2712_TOPRGU_APMIXED_SW_RST 10 > + > +#define MT2712_TOPRGU_SW_RST_NUM 10 Setting rcdev->nr_resets to 10 will make the check in of_reset_simple_xlate() fail for MT2712_TOPRGU_APMIXED_SW_RST. > + > +#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2712 */ > diff --git a/include/dt-bindings/reset-controller/mt8183-resets.h b/include/dt-bindings/reset-controller/mt8183-resets.h > index 8804e34ebdd4..d582da6bedae 100644 > --- a/include/dt-bindings/reset-controller/mt8183-resets.h > +++ b/include/dt-bindings/reset-controller/mt8183-resets.h > @@ -78,4 +78,19 @@ > #define MT8183_INFRACFG_AO_I2C7_SW_RST 126 > #define MT8183_INFRACFG_AO_I2C8_SW_RST 127 > > +#define MT8183_TOPRGU_MM_SW_RST 1 > +#define MT8183_TOPRGU_MFG_SW_RST 2 > +#define MT8183_TOPRGU_VENC_SW_RST 3 > +#define MT8183_TOPRGU_VDEC_SW_RST 4 > +#define MT8183_TOPRGU_IMG_SW_RST 5 > +#define MT8183_TOPRGU_MD_SW_RST 7 > +#define MT8183_TOPRGU_CONN_SW_RST 9 > +#define MT8183_TOPRGU_CONN_MCU_SW_RST 12 > +#define MT8183_TOPRGU_IPU0_SW_RST 14 > +#define MT8183_TOPRGU_IPU1_SW_RST 15 > +#define MT8183_TOPRGU_AUDIO_SW_RST 17 > +#define MT8183_TOPRGU_CAMSYS_SW_RST 18 > + > +#define MT8183_TOPRGU_SW_RST_NUM 18 Same here. If the driver uses the default of_xlate function, this has to be larger than the index of the last reset. regards Philipp _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org https://mailman.alsa-project.org/mailman/listinfo/alsa-devel