From: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
To: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: devicetree <devicetree@vger.kernel.org>,
ALSA Development Mailing List <alsa-devel@alsa-project.org>,
Banajit Goswami <bgoswami@codeaurora.org>,
Venkata Prasad Potturu <quic_potturu@quicinc.com>,
linux-arm-msm@vger.kernel.org, plai@codeaurora.org,
Takashi Iwai <tiwai@suse.com>, Andy Gross <agross@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Mark Brown <broonie@kernel.org>,
Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
rohitkr@codeaurora.org, Stephen Boyd <swboyd@chromium.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
judyhsiao@chromium.org, Linus Walleij <linus.walleij@linaro.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 3/5] pinctrl: qcom: Extract chip specific LPASS LPI code
Date: Tue, 14 Dec 2021 22:52:08 +0530 [thread overview]
Message-ID: <4bcfadd0-8abb-e9e9-ad18-a5b1d3d46308@quicinc.com> (raw)
In-Reply-To: <CAHp75VdL3hmr23CcJLDpvbHaKv5HrDZjmVQpCnRNmPM7nEx6WQ@mail.gmail.com>
On 12/14/2021 10:46 PM, Andy Shevchenko wrote:
> On Tue, Dec 14, 2021 at 7:15 PM Srinivasa Rao Mandadapu
> <quic_srivasam@quicinc.com> wrote:
>> On 12/8/2021 11:58 AM, Andy Shevchenko wrote:
> ...
>
>>>> +#define NO_SLEW -1
>>> Naming sucks for the header.
>>>
>>> LPI_NO_SLEW ?
>> Actually it's already mainline code. Just these patches are
>> rearrangement of old code.
>>
>> still do you suggest to change?
> I would, but this means it should be in a separate change.
>
> ...
Yes. Will do it separate patch later.
>
>>>> +struct lpi_pingroup {
>>>> + const char *name;
>>>> + const unsigned int *pins;
>>>> + unsigned int npins;
>>>> + unsigned int pin;
>>>> + /* Bit offset in slew register for SoundWire pins only */
>>>> + int slew_offset;
>>>> + unsigned int *funcs;
>>>> + unsigned int nfuncs;
>>>> +};
>>> Are you going to convert this to use struct group_desc?
> Any comments on this? It sounds like further improvements.
Actually this also needs as separate patch. these patches will do as
separate series.
>
next prev parent reply other threads:[~2021-12-14 17:23 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-12-07 15:35 [PATCH v5 0/5] Add pin control support for lpass sc7280 Srinivasa Rao Mandadapu
2021-12-07 15:35 ` [PATCH v5 1/5] dt-bindings: pinctrl: qcom: Update lpass lpi file name to SoC specific Srinivasa Rao Mandadapu
2021-12-10 21:15 ` Rob Herring
2021-12-07 15:35 ` [PATCH v5 2/5] dt-bindings: pinctrl: qcom: Add sc7280 lpass lpi pinctrl bindings Srinivasa Rao Mandadapu
2021-12-08 9:24 ` Srinivas Kandagatla
2021-12-08 10:11 ` Srinivasa Rao Mandadapu
2021-12-10 21:17 ` Rob Herring
2021-12-10 21:18 ` Rob Herring
2021-12-07 15:35 ` [PATCH v5 3/5] pinctrl: qcom: Extract chip specific LPASS LPI code Srinivasa Rao Mandadapu
2021-12-08 6:28 ` Andy Shevchenko
2021-12-14 17:15 ` Srinivasa Rao Mandadapu
2021-12-14 17:16 ` Andy Shevchenko
2021-12-14 17:22 ` Srinivasa Rao Mandadapu [this message]
2021-12-14 17:37 ` Andy Shevchenko
2021-12-07 15:35 ` [PATCH v5 4/5] pinctrl: qcom: Add SC7280 lpass pin configuration Srinivasa Rao Mandadapu
2021-12-07 15:35 ` [PATCH v5 5/5] pinctrl: qcom: Update clock voting as optional Srinivasa Rao Mandadapu
2021-12-15 1:28 ` [PATCH v5 0/5] Add pin control support for lpass sc7280 Stephen Boyd
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