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Thu, 10 Nov 2022 05:05:53 -0800 (PST) MIME-Version: 1.0 References: <20221018-clk-range-checks-fixes-v2-0-f6736dec138e@cerno.tech> <20221018-clk-range-checks-fixes-v2-35-f6736dec138e@cerno.tech> In-Reply-To: From: Ulf Hansson Date: Thu, 10 Nov 2022 14:05:16 +0100 Message-ID: Subject: Re: [PATCH v2 35/65] clk: ux500: sysctrl: Add a determine_rate hook To: Linus Walleij Content-Type: text/plain; charset="UTF-8" X-Mailman-Approved-At: Thu, 10 Nov 2022 20:06:20 +0100 Cc: Alexandre Belloni , Prashant Gaikwad , Geert Uytterhoeven , Liam Girdwood , Michael Turquette , Sekhar Nori , Alexandre Torgue , dri-devel@lists.freedesktop.org, Paul Cercueil , Max Filippov , Thierry Reding , linux-phy@lists.infradead.org, David Airlie , Fabio Estevam , linux-stm32@st-md-mailman.stormreply.com, Abel Vesa , Kishon Vijay Abraham I , Samuel Holland , Chunyan Zhang , Takashi Iwai , linux-tegra@vger.kernel.org, Jernej Skrabec , Jonathan Hunter , Chen-Yu Tsai , NXP Linux Team , Orson Zhai , linux-mips@vger.kernel.org, Luca Ceresoli , linux-sunxi@lists.linux.dev, linux-rtc@vger.kernel.org, linux-clk@vger.kernel.org, Charles Keepax , Daniel Vetter , alsa-devel@alsa-project.org, Manivannan Sadhasivam , linux-kernel@vger.kernel.org, Sascha Hauer , linux-actions@lists.infradead.org, Richard Fitzgerald , Mark Brown , linux-mediatek@lists.infradead.org, Maxime Ripard , Baolin Wang , Matthias Brugger , Pengutronix Kernel Team , linux-arm-kernel@lists.infradead.org, AngeloGioacchino Del Regno , Alessandro Zummo , Stephen Boyd , patches@opensource.cirrus.com, Peter De Schrijver , Nicolas Ferre , =?UTF-8?Q?Andreas_F=C3=A4rber?= , linux-renesas-soc@vger.kernel.org, Dinh Nguyen , Vinod Koul , Maxime Coquelin , David Lechner , Shawn Guo , Claudiu Beznea X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" On Thu, 10 Nov 2022 at 12:39, Linus Walleij wrote: > > On Thu, Nov 10, 2022 at 12:29 PM Ulf Hansson wrote: > > On Fri, 4 Nov 2022 at 14:32, Maxime Ripard wrote: > > > > > > The UX500 sysctrl "set_parent" clocks implement a mux with a set_parent > > > hook, but doesn't provide a determine_rate implementation. > > > > > > This is a bit odd, since set_parent() is there to, as its name implies, > > > change the parent of a clock. However, the most likely candidate to > > > trigger that parent change is a call to clk_set_rate(), with > > > determine_rate() figuring out which parent is the best suited for a > > > given rate. > > > > > > The other trigger would be a call to clk_set_parent(), but it's far less > > > used, and it doesn't look like there's any obvious user for that clock. > > > > If I recall correctly, that is the use case we did target for these > > types of clocks. See sound/soc/ux500/ux500_ab85xx.c, for example. > > Hm I am trying to get that driver to work ... from time to time. > It's just that ALSA SoC DT has changed to much that it turns out > into a complete rewrite :/ > > So in sound/soc/ux500/mop500_ab8500.c > I see this: > > status = clk_set_parent(drvdata->clk_ptr_intclk, clk_ptr); > if (status) > (...) > > and there is elaborate code to switch between "SYSCLK" and > "ULPCLK" (ulta-low power clock). Just like you say... however > a clock named SYSCLK or ULPCLK does not appear in the > code in drivers/clk/ux500 or any DT bindings so... it seems to > be non-working for the time being. It's definitely not working, but the corresponding clocks ("ulpclk", "intclk", "audioclk", etc) are being registered in ab8500_reg_clks(). What seems to be missing is a DT conversion for these clocks, so they can be consumed properly. Right? Kind regards Uffe