From: "Viorel Suman (OSS)" <viorel.suman@oss.nxp.com>
To: Nicolin Chen <nicoleotsuka@gmail.com>,
"Viorel Suman (OSS)" <viorel.suman@oss.nxp.com>
Cc: "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"alsa-devel@alsa-project.org" <alsa-devel@alsa-project.org>,
Matthias Schiffer <matthias.schiffer@ew.tq-group.com>,
Timur Tabi <timur@kernel.org>, Xiubo Li <Xiubo.Lee@gmail.com>,
Shengjiu Wang <shengjiu.wang@gmail.com>,
"linuxppc-dev@lists.ozlabs.org" <linuxppc-dev@lists.ozlabs.org>,
Takashi Iwai <tiwai@suse.com>, Rob Herring <robh+dt@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Viorel Suman <viorel.suman@gmail.com>,
Mark Brown <broonie@kernel.org>, dl-linux-imx <linux-imx@nxp.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Cosmin-Gabriel Samoila <cosmin.samoila@nxp.com>,
Fabio Estevam <festevam@gmail.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 1/2] ASoC: fsl_xcvr: Add XCVR ASoC CPU DAI driver
Date: Fri, 18 Sep 2020 14:21:31 +0000 [thread overview]
Message-ID: <VI1PR0401MB2272659A8126D01D9A53F7C5923F0@VI1PR0401MB2272.eurprd04.prod.outlook.com> (raw)
In-Reply-To: <20200917071431.GA17970@Asurada-Nvidia>
Hi Nicolin,
Thank you for your review.
> > +static const u32 fsl_xcvr_earc_channels[] = { 1, 2, 8, 16, 32, }; /*
> > +one bit 6, 12 ? */
>
> What's the meaning of the comments?
Just a thought noted as comment. HDMI2.1 spec defines 6- and 12-channels layout when
one bit audio stream is transmitted - I was wandering how can this be enforced. Is a @todo like of comment.
>
> > +static const int fsl_xcvr_phy_arc_cfg[] = {
> > + FSL_XCVR_PHY_CTRL_ARC_MODE_SE_EN,
> FSL_XCVR_PHY_CTRL_ARC_MODE_CM_EN,
> > +};
>
> Nit: better be u32 vs. int?
Yes, will fix it in v2.
>
> > +/** phy: true => phy, false => pll */ static int
> > +fsl_xcvr_ai_write(struct fsl_xcvr *xcvr, u8 reg, u32 data, bool phy)
> > +{
> > + u32 val, idx, tidx;
> > +
> > + idx = BIT(phy ? 26 : 24);
> > + tidx = BIT(phy ? 27 : 25);
> > +
> > + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_CLR, 0xFF);
> > + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_SET, reg);
> > + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_WDATA, data);
> > + regmap_write(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL_TOG, idx);
> > +
> > + do {
> > + regmap_read(xcvr->regmap, FSL_XCVR_PHY_AI_CTRL, &val);
> > + } while ((val & idx) != ((val & tidx) >> 1));
>
> Might regmap_read_poll_timeout() be better? And it seems to poll intentionally
> with no sleep nor timeout -- would be nice to have a line of comments to explain
> why.
No particular reason to do it with no sleep or timeout here, will check and fix it in v2.
>
> > > +static int fsl_xcvr_runtime_resume(struct device *dev)
> > +{
> > + struct fsl_xcvr *xcvr = dev_get_drvdata(dev);
> > + int ret;
> > +
> > + ret = clk_prepare_enable(xcvr->ipg_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to start IPG clock.\n");
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(xcvr->pll_ipg_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to start PLL IPG clock.\n");
>
> Should it disable ipg_clk?
Yes, thank you, will fix in v2.
>
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(xcvr->phy_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to start PHY clock: %d\n", ret);
> > + clk_disable_unprepare(xcvr->ipg_clk);
>
> Should it disable pll_ipg_clk?
Yes, will fix in v2.
>
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(xcvr->spba_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to start SPBA clock.\n");
> > + clk_disable_unprepare(xcvr->phy_clk);
> > + clk_disable_unprepare(xcvr->ipg_clk);
>
> Ditto
Ok.
>
> > + return ret;
> > + }
> > +
> > + regcache_cache_only(xcvr->regmap, false);
> > + regcache_mark_dirty(xcvr->regmap);
> > + ret = regcache_sync(xcvr->regmap);
> > +
> > + if (ret) {
> > + dev_err(dev, "failed to sync regcache.\n");
> > + return ret;
>
> What about those clocks? Probably better to have some error-out labels at the
> end of the function?
Make sense, will fix in v2.
>
> > + }
> > +
> > + reset_control_assert(xcvr->reset);
> > + reset_control_deassert(xcvr->reset);
> > +
> > + ret = fsl_xcvr_load_firmware(xcvr);
> > + if (ret) {
> > + dev_err(dev, "failed to load firmware.\n");
> > + return ret;
>
> Ditto
>
> > + }
> > +
> > + /* Release M0+ reset */
> > + ret = regmap_update_bits(xcvr->regmap, FSL_XCVR_EXT_CTRL,
> > + FSL_XCVR_EXT_CTRL_CORE_RESET, 0);
> > + if (ret < 0) {
> > + dev_err(dev, "M0+ core release failed: %d\n", ret);
> > + return ret;
>
> Ditto
>
> > + }
> > + mdelay(50);
>
> Any reason to use mdelay over msleep for a 50ms wait? May add a line of
> comments if mdelay is a must?
No particular reason, will fix it in v2.
Thank you,
Viorel
next prev parent reply other threads:[~2020-09-18 14:22 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-16 9:17 [PATCH 0/2] DAI driver for new XCVR IP Viorel Suman (OSS)
2020-09-16 9:17 ` [PATCH 1/2] ASoC: fsl_xcvr: Add XCVR ASoC CPU DAI driver Viorel Suman (OSS)
2020-09-17 7:14 ` Nicolin Chen
2020-09-18 14:21 ` Viorel Suman (OSS) [this message]
2020-09-18 16:06 ` Timur Tabi
2020-09-17 13:53 ` Mark Brown
2020-09-18 15:02 ` Viorel Suman (OSS)
2020-09-18 15:20 ` Mark Brown
2020-09-18 15:33 ` Viorel Suman (OSS)
2020-09-16 9:17 ` [PATCH 2/2] ASoC: dt-bindings: fsl_xcvr: Add document for XCVR Viorel Suman (OSS)
2020-09-18 17:23 ` Rob Herring
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