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Wed, 29 Jul 2020 07:31:06 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 29 Jul 2020 07:31:05 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 29 Jul 2020 07:31:05 -0500 Received: from [10.250.35.195] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 06TCV5XV010018; Wed, 29 Jul 2020 07:31:05 -0500 Subject: Re: [PATCH 3/3] ASoC: codec: tlv3204: Moving GPIO reset and add ADC reset To: Michael Sit Wei Hong , References: <20200729073256.24028-1-michael.wei.hong.sit@intel.com> <20200729073256.24028-4-michael.wei.hong.sit@intel.com> From: Dan Murphy Message-ID: Date: Wed, 29 Jul 2020 07:31:00 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200729073256.24028-4-michael.wei.hong.sit@intel.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: cezary.rojewski@intel.com, a-estrada@ti.com, andriy.shevchenko@intel.com, tiwai@suse.com, jee.heng.sia@intel.com, pierre-louis.bossart@linux.intel.com, liam.r.girdwood@linux.intel.com, broonie@kernel.org, zakkaye@ti.com X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: alsa-devel-bounces@alsa-project.org Sender: "Alsa-devel" Hello On 7/29/20 2:32 AM, Michael Sit Wei Hong wrote: > Moving GPIO reset to a later stage and before clock registration to > ensure that the host system and codec clocks are in sync. If the host > register clock values prior to gpio reset, the last configured codec clock > is registered to the host. The codec then gets gpio resetted setting the > codec clocks to their default value, causing a mismatch. Host system will > skip clock setting thinking the codec clocks are already at the requested > rate. > > ADC reset is added to ensure the next audio capture does not have > undesired artifacts. It is probably related to the original code > where the probe function resets the ADC prior to 1st record. > > Signed-off-by: Michael Sit Wei Hong > Reviewed-by: Sia Jee Heng > Reviewed-by: Pierre-Louis Bossart > --- > sound/soc/codecs/tlv320aic32x4.c | 47 ++++++++++++++++++++++++-------- > 1 file changed, 35 insertions(+), 12 deletions(-) > > diff --git a/sound/soc/codecs/tlv320aic32x4.c b/sound/soc/codecs/tlv320aic32x4.c > index 5af438a00f95..37e14558d7c0 100644 > --- a/sound/soc/codecs/tlv320aic32x4.c > +++ b/sound/soc/codecs/tlv320aic32x4.c > @@ -50,6 +50,28 @@ struct aic32x4_priv { > struct device *dev; > }; > > +static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w, > + struct snd_kcontrol *kcontrol, int event) > +{ > + struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm); > + u32 adc_reg; > + > + /* > + * Workaround: the datasheet does not mention a required programming > + * sequence but experiments show the ADC needs to be reset after each > + * capture to avoid audible artifacts. > + */ > + switch (event) { > + case SND_SOC_DAPM_POST_PMD: > + adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP); This gives me a build error sound/soc/codecs/tlv320aic32x4.c: In function ‘aic32x4_reset_adc’: sound/soc/codecs/tlv320aic32x4.c:66:13: error: implicit declaration of function ‘snd_soc_component_read32’; did you mean ‘snd_soc_component_read’? [-Werror=implicit-function-declaration]    66 |   adc_reg = snd_soc_component_read32(component, AIC32X4_ADCSETUP);       |             ^~~~~~~~~~~~~~~~~~~~~~~~       |             snd_soc_component_read Also you should check the return to make sure it is valid. Dan