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Received: from BN8PR12MB3300.namprd12.prod.outlook.com (20.179.66.160) by BN8PR12MB3012.namprd12.prod.outlook.com (20.178.209.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.13; Wed, 15 Jan 2020 02:56:05 +0000 Received: from BN8PR12MB3300.namprd12.prod.outlook.com ([fe80::846f:2b61:2803:e80]) by BN8PR12MB3300.namprd12.prod.outlook.com ([fe80::846f:2b61:2803:e80%5]) with mapi id 15.20.2623.015; Wed, 15 Jan 2020 02:56:05 +0000 Date: Wed, 15 Jan 2020 10:55:57 +0800 From: Huang Rui To: "Kuehling, Felix" Subject: Re: [PATCH 1/5] drm/amdgpu: only set cp active field for kiq queue Message-ID: <20200115025556.GA6788@jenkins-Celadon-RN> References: <1578638233-9357-1-git-send-email-ray.huang@amd.com> <20200114093640.GA20112@jenkins-Celadon-RN> Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-ClientProxiedBy: HK0PR01CA0069.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::33) To BN8PR12MB3300.namprd12.prod.outlook.com (2603:10b6:408:6a::32) MIME-Version: 1.0 Received: from jenkins-Celadon-RN (180.167.199.189) by HK0PR01CA0069.apcprd01.prod.exchangelabs.com (2603:1096:203:a6::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2623.10 via Frontend Transport; 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X-Microsoft-Antispam-Message-Info: FJctdC205/9j/zAOX5H2Shwg2tLvtvH/phNaiOWYMRl4JyrjFrW+2df2YeLxtHxpU4iZiT1dUOZgHiQ+U6+jhyYNn4OPx78agK+gLVZlbGcrjmdiDQwvODY1ohe9kBUhgmpi/PZEJ2ju688Emfltee4fuj8msJ0rR9OiGBUxfIJh8MOkW8clZSIf7qUthuVy/KesjUqSP8YK0xxpvKFmWR3FTiEm99Tc3VxV0ycmvjUQKqPbW4Afkjju5JZ4IQMXkzgVf50MPTWJRfOrRk5eB+d3YGNPHdDOzxiaj8ECSSw9eLsbgJtuupDvhe8UxPwltSEXXAlYDei5YZSLLQ7/Rm6k9Yb9GI7b5Yv5bgRfWkBpXVBXvOsjcRPalipuxYViQyIy7YVtDhkkNaB3WJZ/OydzjmRB94tktfesTz/nEig7i+yozOJ61T4kHSN2UUxm X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1d0dfde8-4d47-436c-dfcd-08d7996676c0 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jan 2020 02:56:05.5599 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: q4z05LWwdD3UJL4ZzGMW/IECkHCl1kFzzNEXoeavpzpKUiIBiFYdMdXl8psJ11VtMSYkBKrYTDKdQo34x+aRgw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB3012 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Deucher, Alexander" , "amd-gfx@lists.freedesktop.org" Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On Tue, Jan 14, 2020 at 11:30:15PM +0800, Kuehling, Felix wrote: > Patch 1 is > = > Reviewed-by: Felix Kuehling > = > Patches 2 and 3 should be squashed. In that case they are > = > Reviewed-by: Felix Kuehling > = > Patches 4 and 5 need to be tested. I think you mentioned GFX10 worked = > (patch 4) but GFX8 was failing (patch 5). Have you found the problem? I = > haven't seen any update to the patch. Yes, GFX8 (patch5) failed with the page fault, I am still looking at this issue. For other patches (verified good), I have pushed into drm-next. Thanks, Ray > = > Regards, > =A0 Felix > = > On 2020-01-14 4:36, Huang Rui wrote: > > Ping~ > > > > On Fri, Jan 10, 2020 at 02:37:09PM +0800, Huang, Ray wrote: > >> The mec ucode will set the CP_HQD_ACTIVE bit while the queue is mapped= by > >> MAP_QUEUES packet. So we only need set cp active field for kiq queue. > >> > >> Signed-off-by: Huang Rui > >> --- > >> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 +++++-- > >> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 7 +++++-- > >> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 7 +++++-- > >> 3 files changed, 15 insertions(+), 6 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/= amd/amdgpu/gfx_v10_0.c > >> index 5b05334..22c69d8 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > >> @@ -3323,8 +3323,11 @@ static int gfx_v10_0_compute_mqd_init(struct am= dgpu_ring *ring) > >> tmp =3D REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); > >> mqd->cp_hqd_ib_control =3D tmp; > >> = > >> - /* activate the queue */ > >> - mqd->cp_hqd_active =3D 1; > >> + /* map_queues packet doesn't need activate the queue, > >> + * so only kiq need set this field. > >> + */ > >> + if (ring->funcs->type =3D=3D AMDGPU_RING_TYPE_KIQ) > >> + mqd->cp_hqd_active =3D 1; > >> = > >> return 0; > >> } > >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/a= md/amdgpu/gfx_v8_0.c > >> index 8b9f440..306ee61 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > >> @@ -4558,8 +4558,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring= *ring) > >> mqd->cp_hqd_eop_wptr_mem =3D RREG32(mmCP_HQD_EOP_WPTR_MEM); > >> mqd->cp_hqd_eop_dones =3D RREG32(mmCP_HQD_EOP_DONES); > >> = > >> - /* activate the queue */ > >> - mqd->cp_hqd_active =3D 1; > >> + /* map_queues packet doesn't need activate the queue, > >> + * so only kiq need set this field. > >> + */ > >> + if (ring->funcs->type =3D=3D AMDGPU_RING_TYPE_KIQ) > >> + mqd->cp_hqd_active =3D 1; > >> = > >> return 0; > >> } > >> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/a= md/amdgpu/gfx_v9_0.c > >> index 45328f9..e29818b 100644 > >> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > >> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > >> @@ -3313,8 +3313,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring= *ring) > >> tmp =3D REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3); > >> mqd->cp_hqd_ib_control =3D tmp; > >> = > >> - /* activate the queue */ > >> - mqd->cp_hqd_active =3D 1; > >> + /* map_queues packet doesn't need activate the queue, > >> + * so only kiq need set this field. > >> + */ > >> + if (ring->funcs->type =3D=3D AMDGPU_RING_TYPE_KIQ) > >> + mqd->cp_hqd_active =3D 1; > >> = > >> return 0; > >> } > >> -- = > >> 2.7.4 > >> _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx