From: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: sunpeng.li@amd.com, rodrigo.siqueira@amd.com,
harry.wentland@amd.com,
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Subject: [PATCH 04/22] drm/amd/display: Get fb base and fb offset for DMUB from registers
Date: Thu, 16 Jan 2020 15:14:00 -0500 [thread overview]
Message-ID: <20200116201418.2254-5-Bhawanpreet.Lakha@amd.com> (raw)
In-Reply-To: <20200116201418.2254-1-Bhawanpreet.Lakha@amd.com>
From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
[Why]
Under some hardware initialization sequences the fb base/fb offset
provided can be zero or hardwareinit can happen too late.
We want to ensure that we always have the correct fb_base/fb_offset
when performing DMCUB hardware initialization so we can do DMCUB
command table offloading during first dc hardware init.
[How]
Read from the DCN registers. VBIOS already filled these in for us.
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
---
.../gpu/drm/amd/display/dmub/inc/dmub_srv.h | 2 ++
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.c | 21 +++++++++++++++++--
.../gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 8 +++++--
3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
index 8e23a7017588..287fb9a36a64 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_srv.h
@@ -231,6 +231,8 @@ struct dmub_srv_base_funcs {
struct dmub_srv_hw_funcs {
/* private: internal use only */
+ void (*init)(struct dmub_srv *dmub);
+
void (*reset)(struct dmub_srv *dmub);
void (*reset_release)(struct dmub_srv *dmub);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index cd51c6138894..9229012b93e2 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -54,6 +54,19 @@ const struct dmub_srv_common_regs dmub_srv_dcn20_regs = {
/* Shared functions. */
+static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
+ uint64_t *fb_base,
+ uint64_t *fb_offset)
+{
+ uint32_t tmp;
+
+ REG_GET(DCN_VM_FB_LOCATION_BASE, FB_BASE, &tmp);
+ *fb_base = (uint64_t)tmp << 24;
+
+ REG_GET(DCN_VM_FB_OFFSET, FB_OFFSET, &tmp);
+ *fb_offset = (uint64_t)tmp << 24;
+}
+
static inline void dmub_dcn20_translate_addr(const union dmub_addr *addr_in,
uint64_t fb_base,
uint64_t fb_offset,
@@ -82,7 +95,9 @@ void dmub_dcn20_backdoor_load(struct dmub_srv *dmub,
const struct dmub_window *cw1)
{
union dmub_addr offset;
- uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+ uint64_t fb_base, fb_offset;
+
+ dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
REG_UPDATE(DMCUB_SEC_CNTL, DMCUB_SEC_RESET, 1);
REG_UPDATE_2(DMCUB_MEM_CNTL, DMCUB_MEM_READ_SPACE, 0x3,
@@ -118,7 +133,9 @@ void dmub_dcn20_setup_windows(struct dmub_srv *dmub,
const struct dmub_window *cw6)
{
union dmub_addr offset;
- uint64_t fb_base = dmub->fb_base, fb_offset = dmub->fb_offset;
+ uint64_t fb_base, fb_offset;
+
+ dmub_dcn20_get_fb_base_offset(dmub, &fb_base, &fb_offset);
dmub_dcn20_translate_addr(&cw2->offset, fb_base, fb_offset, &offset);
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
index 53bfd4da69ad..04b0fa13153d 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h
@@ -92,7 +92,9 @@ struct dmub_srv;
DMUB_SR(DMCUB_SCRATCH14) \
DMUB_SR(DMCUB_SCRATCH15) \
DMUB_SR(CC_DC_PIPE_DIS) \
- DMUB_SR(MMHUBBUB_SOFT_RESET)
+ DMUB_SR(MMHUBBUB_SOFT_RESET) \
+ DMUB_SR(DCN_VM_FB_LOCATION_BASE) \
+ DMUB_SR(DCN_VM_FB_OFFSET)
#define DMUB_COMMON_FIELDS() \
DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \
@@ -121,7 +123,9 @@ struct dmub_srv;
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_TOP_ADDRESS) \
DMUB_SF(DMCUB_REGION4_TOP_ADDRESS, DMCUB_REGION4_ENABLE) \
DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \
- DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET)
+ DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \
+ DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \
+ DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET)
struct dmub_srv_common_reg_offset {
#define DMUB_SR(reg) uint32_t reg;
--
2.17.1
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next prev parent reply other threads:[~2020-01-16 20:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-16 20:13 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
2020-01-16 20:13 ` [PATCH 01/22] drm/amd/display: update MSA and VSC SDP on video test pattern request Bhawanpreet Lakha
2020-01-16 20:13 ` [PATCH 02/22] drm/amd/display: Do not send training pattern if VS Different Bhawanpreet Lakha
2020-01-16 20:13 ` [PATCH 03/22] drm/amd/display: Add debug option to disable DSC support Bhawanpreet Lakha
2020-01-16 20:14 ` Bhawanpreet Lakha [this message]
2020-01-16 20:14 ` [PATCH 05/22] drm/amd/display: Fallback to DMCUB when command table is missing Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 06/22] drm/amd/display: check pipe_ctx is split pipe or not Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 07/22] drm/amd/display: Fixed comment styling Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 08/22] drm/amd/display: Do DMCUB hw_init before DC Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 09/22] drm/amd/display: Fix DML dummyinteger types mismatch Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 10/22] drm/amd/display: Refactor to remove diags specific rgam func Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 11/22] drm/amd/display: Refine i2c frequency calculating sequence Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 12/22] drm/amd/display: 3.2.69 Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 13/22] drm/amd/display: fix rotation_angle to use enum values Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 14/22] drm/amd/display: Fix update type for multiple planes Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 15/22] drm/amd/display: Add hardware reset interface for DMUB service Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 16/22] drm/amd/display: Call ATOM_INIT instead of ATOM_ENABLE for DMCUB Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 17/22] drm/amd/display: Reset inbox rptr/wptr when resetting DMCUB Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 18/22] drm/amd/display: Check hw_init state when determining if DMCUB is initialized Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 19/22] drm/amd/display: support VSC SDP update on video test pattern request Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 20/22] drm/amd/display: changed max_downscale_src_width to 4096 Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 21/22] drm/amd/display: init hw i2c speed Bhawanpreet Lakha
2020-01-16 20:14 ` [PATCH 22/22] drm/amd/display: use odm combine for YCbCr420 timing with h_active greater than 4096 Bhawanpreet Lakha
-- strict thread matches above, loose matches on Subject: below --
2020-01-16 20:10 [PATCH 00/22] DC Patches 16 Jan 2020 Bhawanpreet Lakha
2020-01-16 20:10 ` [PATCH 04/22] drm/amd/display: Get fb base and fb offset for DMUB from registers Bhawanpreet Lakha
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