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From: Alex Sierra <alex.sierra@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Sierra <alex.sierra@amd.com>
Subject: [PATCH 3/4] drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5
Date: Fri, 27 Mar 2020 14:37:46 -0500	[thread overview]
Message-ID: <20200327193747.8520-3-alex.sierra@amd.com> (raw)
In-Reply-To: <20200327193747.8520-1-alex.sierra@amd.com>

[Why]
Due Page faults can easily overwhelm the interrupt handler.
So to make sure that we never lose valuable interrupts on the primary ring
we re-route page faults to IH ring 1.
It also facilitates the recovery page process, since it's already
running from a process context.
This is valid for Arcturus and future Navi generation GPUs.

[How]
Setting IH_CLIENT_CFG_DATA for VMC and UMD IH clients.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index 4ce42635787a..6fca5206833d 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -205,6 +205,24 @@ static uint32_t navi10_ih_doorbell_rptr(struct amdgpu_ih_ring *ih)
 	return ih_doorbell_rtpr;
 }
 
+static void navi10_ih_reroute_ih(struct amdgpu_device *adev)
+{
+	uint32_t tmp;
+
+	/* Reroute to IH ring 1 for VMC */
+	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x12);
+	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+
+	/* Reroute IH ring 1 for UMC */
+	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_INDEX, 0x1B);
+	tmp = RREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA);
+	tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
+	WREG32_SOC15(OSSSYS, 0, mmIH_CLIENT_CFG_DATA, tmp);
+}
+
 /**
  * navi10_ih_irq_init - init and enable the interrupt ring
  *
@@ -243,6 +261,7 @@ static int navi10_ih_irq_init(struct amdgpu_device *adev)
 	} else {
 		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);
 	}
+	navi10_ih_reroute_ih(adev);
 
 	if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT)) {
 		if (ih->use_bus_addr) {
-- 
2.17.1

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  parent reply	other threads:[~2020-03-27 19:38 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-27 19:37 [PATCH 1/4] drm/amdgpu: enable IH ring 1 and ring 2 for navi Alex Sierra
2020-03-27 19:37 ` [PATCH 2/4] drm/amdgpu: call psp to program ih cntl in SR-IOV for Navi Alex Sierra
2020-03-27 19:37 ` Alex Sierra [this message]
2020-03-27 19:37 ` [PATCH 4/4] drm/amdgpu: replace ih ip block for vega20 and arcturus Alex Sierra
2020-03-27 19:55   ` Felix Kuehling
  -- strict thread matches above, loose matches on Subject: below --
2020-03-24 21:57 [PATCH 1/4] drm/amdgpu: enable IH ring 1 and ring 2 for navi Alex Sierra
2020-03-24 21:57 ` [PATCH 3/4] drm/amdgpu: reroute VMC and UMD to IH ring 1 for oss v5 Alex Sierra

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