* [PATCH 2/2] drm/amd/powerplay: update driver if file for sienna_cichlid
2020-06-24 6:35 [PATCH 1/2] drm/amd/powerplay: change method to set board parameters Likun Gao
@ 2020-06-24 6:35 ` Likun Gao
2020-06-24 13:58 ` [PATCH 1/2] drm/amd/powerplay: change method to set board parameters Deucher, Alexander
1 sibling, 0 replies; 3+ messages in thread
From: Likun Gao @ 2020-06-24 6:35 UTC (permalink / raw)
To: amd-gfx; +Cc: Likun Gao, Kenneth Feng, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Update sienna_cichlid driver if header file to match pptable changes.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Change-Id: Idcc081797f54509ea57503cce1dc915f718f189e
---
.../powerplay/inc/smu11_driver_if_sienna_cichlid.h | 12 ++++++++----
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h | 2 +-
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 7 +------
3 files changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
index 5322f6da3071..302c2bcf9404 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
@@ -27,7 +27,7 @@
// *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if
// any structure is changed in this file
-#define SMU11_DRIVER_IF_VERSION 0x31
+#define SMU11_DRIVER_IF_VERSION 0x32
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
@@ -865,8 +865,7 @@ typedef struct {
uint16_t DfllGfxclkSpreadFreq; // kHz
// UCLK Spread Spectrum
- uint8_t UclkSpreadEnabled; // on or off
- uint8_t UclkSpreadPercent; // Q4.4
+ uint16_t UclkSpreadPadding;
uint16_t UclkSpreadFreq; // kHz
// FCLK Spread Spectrum
@@ -896,8 +895,11 @@ typedef struct {
uint8_t VddqOffEnabled;
uint8_t PaddingUmcFlags[2];
+ // UCLK Spread Spectrum
+ uint8_t UclkSpreadPercent[16];
+
// SECTION: Board Reserved
- uint32_t BoardReserved[15];
+ uint32_t BoardReserved[11];
// SECTION: Structure Padding
@@ -936,10 +938,12 @@ typedef struct {
int16_t OverDrivePct; // %
uint16_t FanMaximumRpm;
uint16_t FanMinimumPwm;
+ uint16_t FanAcousticLimitRpm;
uint16_t FanTargetTemperature; // Degree Celcius
uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
uint16_t MaxOpTemp; // Degree Celcius
+ uint16_t Padding_16[1];
uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmStopTemp;
uint8_t FanMode;
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
index 4fb911d8b49c..d07bf4fe6e4a 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
@@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
-#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x31
+#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
/* MP Apertures */
#define MP0_Public 0x03800000
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 693ad8963d0a..459a3c62e47b 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -2401,8 +2401,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
- dev_info(smu->adev->dev, "UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled);
- dev_info(smu->adev->dev, "UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
+ dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
@@ -2447,10 +2446,6 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
- dev_info(smu->adev->dev, "BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
- dev_info(smu->adev->dev, "BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
- dev_info(smu->adev->dev, "BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
- dev_info(smu->adev->dev, "BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
--
2.25.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/2] drm/amd/powerplay: change method to set board parameters
2020-06-24 6:35 [PATCH 1/2] drm/amd/powerplay: change method to set board parameters Likun Gao
2020-06-24 6:35 ` [PATCH 2/2] drm/amd/powerplay: update driver if file for sienna_cichlid Likun Gao
@ 2020-06-24 13:58 ` Deucher, Alexander
1 sibling, 0 replies; 3+ messages in thread
From: Deucher, Alexander @ 2020-06-24 13:58 UTC (permalink / raw)
To: Gao, Likun, amd-gfx; +Cc: Feng, Kenneth, Zhang, Hawking
[-- Attachment #1.1: Type: text/plain, Size: 7169 bytes --]
[AMD Public Use]
Series is:
Acked-by: Alex Deucher <alexander.deucher@amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Likun Gao <likun.gao@amd.com>
Sent: Wednesday, June 24, 2020 2:35 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Gao, Likun <Likun.Gao@amd.com>; Feng, Kenneth <Kenneth.Feng@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: [PATCH 1/2] drm/amd/powerplay: change method to set board parameters
From: Likun Gao <Likun.Gao@amd.com>
Copy board parameters directly instead of set each parameter for
sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
---
.../drm/amd/powerplay/sienna_cichlid_ppt.c | 89 +------------------
1 file changed, 2 insertions(+), 87 deletions(-)
diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 769e031d489a..693ad8963d0a 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -394,7 +394,6 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
PPTable_t *smc_pptable = table_context->driver_pptable;
struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
int index, ret;
- int i;
index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
smc_dpm_info);
@@ -405,92 +404,8 @@ static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
return ret;
memcpy(smc_pptable->I2cControllers, smc_dpm_table->I2cControllers,
- sizeof(I2cControllerConfig_t) * NUM_I2C_CONTROLLERS);
-
- /* SVI2 Board Parameters */
- smc_pptable->VddGfxVrMapping = smc_dpm_table->VddGfxVrMapping;
- smc_pptable->VddSocVrMapping = smc_dpm_table->VddSocVrMapping;
- smc_pptable->VddMem0VrMapping = smc_dpm_table->VddMem0VrMapping;
- smc_pptable->VddMem1VrMapping = smc_dpm_table->VddMem1VrMapping;
- smc_pptable->GfxUlvPhaseSheddingMask = smc_dpm_table->GfxUlvPhaseSheddingMask;
- smc_pptable->SocUlvPhaseSheddingMask = smc_dpm_table->SocUlvPhaseSheddingMask;
- smc_pptable->VddciUlvPhaseSheddingMask = smc_dpm_table->VddciUlvPhaseSheddingMask;
- smc_pptable->MvddUlvPhaseSheddingMask = smc_dpm_table->MvddUlvPhaseSheddingMask;
-
- /* Telemetry Settings */
- smc_pptable->GfxMaxCurrent = smc_dpm_table->GfxMaxCurrent;
- smc_pptable->GfxOffset = smc_dpm_table->GfxOffset;
- smc_pptable->Padding_TelemetryGfx = smc_dpm_table->Padding_TelemetryGfx;
- smc_pptable->SocMaxCurrent = smc_dpm_table->SocMaxCurrent;
- smc_pptable->SocOffset = smc_dpm_table->SocOffset;
- smc_pptable->Padding_TelemetrySoc = smc_dpm_table->Padding_TelemetrySoc;
- smc_pptable->Mem0MaxCurrent = smc_dpm_table->Mem0MaxCurrent;
- smc_pptable->Mem0Offset = smc_dpm_table->Mem0Offset;
- smc_pptable->Padding_TelemetryMem0 = smc_dpm_table->Padding_TelemetryMem0;
- smc_pptable->Mem1MaxCurrent = smc_dpm_table->Mem1MaxCurrent;
- smc_pptable->Mem1Offset = smc_dpm_table->Mem1Offset;
- smc_pptable->Padding_TelemetryMem1 = smc_dpm_table->Padding_TelemetryMem1;
- smc_pptable->MvddRatio = smc_dpm_table->MvddRatio;
-
- /* GPIO Settings */
- smc_pptable->AcDcGpio = smc_dpm_table->AcDcGpio;
- smc_pptable->AcDcPolarity = smc_dpm_table->AcDcPolarity;
- smc_pptable->VR0HotGpio = smc_dpm_table->VR0HotGpio;
- smc_pptable->VR0HotPolarity = smc_dpm_table->VR0HotPolarity;
- smc_pptable->VR1HotGpio = smc_dpm_table->VR1HotGpio;
- smc_pptable->VR1HotPolarity = smc_dpm_table->VR1HotPolarity;
- smc_pptable->GthrGpio = smc_dpm_table->GthrGpio;
- smc_pptable->GthrPolarity = smc_dpm_table->GthrPolarity;
-
- /* LED Display Settings */
- smc_pptable->LedPin0 = smc_dpm_table->LedPin0;
- smc_pptable->LedPin1 = smc_dpm_table->LedPin1;
- smc_pptable->LedPin2 = smc_dpm_table->LedPin2;
- smc_pptable->LedEnableMask = smc_dpm_table->LedEnableMask;
- smc_pptable->LedPcie = smc_dpm_table->LedPcie;
- smc_pptable->LedError = smc_dpm_table->LedError;
- smc_pptable->LedSpare1[0] = smc_dpm_table->LedSpare1[0];
- smc_pptable->LedSpare1[1] = smc_dpm_table->LedSpare1[1];
-
- /* GFXCLK PLL Spread Spectrum */
- smc_pptable->PllGfxclkSpreadEnabled = smc_dpm_table->PllGfxclkSpreadEnabled;
- smc_pptable->PllGfxclkSpreadPercent = smc_dpm_table->PllGfxclkSpreadPercent;
- smc_pptable->PllGfxclkSpreadFreq = smc_dpm_table->PllGfxclkSpreadFreq;
-
- /* GFXCLK DFLL Spread Spectrum */
- smc_pptable->DfllGfxclkSpreadEnabled = smc_dpm_table->DfllGfxclkSpreadEnabled;
- smc_pptable->DfllGfxclkSpreadPercent = smc_dpm_table->DfllGfxclkSpreadPercent;
- smc_pptable->DfllGfxclkSpreadFreq = smc_dpm_table->DfllGfxclkSpreadFreq;
-
- /* UCLK Spread Spectrum */
- smc_pptable->UclkSpreadEnabled = smc_dpm_table->UclkSpreadEnabled;
- smc_pptable->UclkSpreadPercent = smc_dpm_table->UclkSpreadPercent;
- smc_pptable->UclkSpreadFreq = smc_dpm_table->UclkSpreadFreq;
-
- /* FCLK Spred Spectrum */
- smc_pptable->FclkSpreadEnabled = smc_dpm_table->FclkSpreadEnabled;
- smc_pptable->FclkSpreadPercent = smc_dpm_table->FclkSpreadPercent;
- smc_pptable->FclkSpreadFreq = smc_dpm_table->FclkSpreadFreq;
-
- /* Memory Config */
- smc_pptable->MemoryChannelEnabled = smc_dpm_table->MemoryChannelEnabled;
- smc_pptable->DramBitWidth = smc_dpm_table->DramBitWidth;
- smc_pptable->PaddingMem1[0] = smc_dpm_table->PaddingMem1[0];
- smc_pptable->PaddingMem1[1] = smc_dpm_table->PaddingMem1[1];
- smc_pptable->PaddingMem1[2] = smc_dpm_table->PaddingMem1[2];
-
- /* Total board power */
- smc_pptable->TotalBoardPower = smc_dpm_table->TotalBoardPower;
- smc_pptable->BoardPowerPadding = smc_dpm_table->BoardPowerPadding;
-
- /* XGMI Training */
- for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++) {
- smc_pptable->XgmiLinkSpeed[i] = smc_dpm_table->XgmiLinkSpeed[i];
- smc_pptable->XgmiLinkWidth[i] = smc_dpm_table->XgmiLinkWidth[i];
- smc_pptable->XgmiFclkFreq[i] = smc_dpm_table->XgmiFclkFreq[i];
- smc_pptable->XgmiSocVoltage[i] = smc_dpm_table->XgmiSocVoltage[i];
- }
-
+ sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
+
return 0;
}
--
2.25.1
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