[PATCH] drm/amdgpu: Adding wait time before reading upll control register

From: Alex Jivin <alex.jivin@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Alex Deucher <alexander.deucher@amd.com>,
	Luben Tuikov <luben.tuikov@amd.com>
Subject: [PATCH] drm/amdgpu: Adding wait time before reading upll control register
Date: Fri, 26 Jun 2020 12:12:39 -0400	[thread overview]
Message-ID: <20200626161239.19762-1-alex.jivin@amd.com> (raw)

Adding a delay between writing to UVD control register and reading from it.
This is to allow the HW to process the write command.

Signed-off-by: Alex Jivin <alex.jivin@amd.com>
Suggested-By: Luben Tukov <luben.tuikov@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 9d7b4ccd17b8..42cdc14fb79d 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1435,6 +1435,12 @@ static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev,
 	/* Assert UPLL_CTLREQ */
 	WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK);
 
+	/* Waiting for HW to process the previous write.
+	 * This is to give a chance to HW to act before
+	 * the first read is done.
+	 */
+	mdelay(1);
+
 	/* Wait for CTLACK and CTLACK2 to get asserted */
 	for (i = 0; i < SI_MAX_CTLACKS_ASSERTION_WAIT; ++i) {
 		uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK;
-- 
2.17.1

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