* [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh
@ 2020-10-27 9:41 Xiaojian Du
2020-10-27 9:41 ` [PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware " Xiaojian Du
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to update the smu v11.5 smc header for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++++++++++--------
1 file changed, 68 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
index 55c1b151a68d..1ada0eb64663 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
@@ -32,55 +32,77 @@
#define PPSMC_Result_CmdRejectedBusy 0xFC
// Message Definitions:
-#define PPSMC_MSG_TestMessage 0x1
-#define PPSMC_MSG_GetSmuVersion 0x2
-#define PPSMC_MSG_GetDriverIfVersion 0x3
-#define PPSMC_MSG_EnableGfxOff 0x4
-#define PPSMC_MSG_DisableGfxOff 0x5
-#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
-#define PPSMC_MSG_PowerUpIspByTile 0x7
-#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
-#define PPSMC_MSG_PowerUpVcn 0x9
-#define PPSMC_MSG_spare 0xA
-#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
-#define PPSMC_MSG_SetMinVideoGfxclkFreq 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
-#define PPSMC_MSG_ActiveProcessNotify 0xD
-#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
-#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
-#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
-#define PPSMC_MSG_SetDriverDramAddrLow 0x11
-#define PPSMC_MSG_TransferTableSmu2Dram 0x12
-#define PPSMC_MSG_TransferTableDram2Smu 0x13
-#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
-#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
-#define PPSMC_MSG_spare1 0x16
-#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
-#define PPSMC_MSG_SetMinVideoFclkFreq 0x18
-#define PPSMC_MSG_SetSoftMinVcn 0x19
-#define PPSMC_MSG_EnablePostCode 0x1A
-#define PPSMC_MSG_GetGfxclkFrequency 0x1B
-#define PPSMC_MSG_GetFclkFrequency 0x1C
-#define PPSMC_MSG_AllowGfxOff 0x1D
-#define PPSMC_MSG_DisallowGfxOff 0x1E
-#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
-#define PPSMC_MSG_SetHardMinGfxClk 0x20
-#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
-#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
-#define PPSMC_MSG_SetSoftMaxVcn 0x23
-#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM
-#define PPSMC_MSG_SetPowerLimitPercentage 0x25
-#define PPSMC_MSG_PowerDownJpeg 0x26
-#define PPSMC_MSG_PowerUpJpeg 0x27
-#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
-#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
-#define PPSMC_MSG_PowerUpCvip 0x2A
-#define PPSMC_MSG_PowerDownCvip 0x2B
-#define PPSMC_Message_Count 0x2C
+#define PPSMC_MSG_TestMessage 0x1
+#define PPSMC_MSG_GetSmuVersion 0x2
+#define PPSMC_MSG_GetDriverIfVersion 0x3
+#define PPSMC_MSG_EnableGfxOff 0x4
+#define PPSMC_MSG_DisableGfxOff 0x5
+#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
+#define PPSMC_MSG_PowerUpIspByTile 0x7
+#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
+#define PPSMC_MSG_PowerUpVcn 0x9
+#define PPSMC_MSG_spare 0xA
+#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
+#define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
+#define PPSMC_MSG_ActiveProcessNotify 0xD
+#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
+#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
+#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
+#define PPSMC_MSG_SetDriverDramAddrLow 0x11
+#define PPSMC_MSG_TransferTableSmu2Dram 0x12
+#define PPSMC_MSG_TransferTableDram2Smu 0x13
+#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
+#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
+#define PPSMC_MSG_spare1 0x16
+#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
+#define PPSMC_MSG_SetSoftMinFclk 0x18 //Used to be PPSMC_MSG_SetMinVideoFclkFreq
+#define PPSMC_MSG_SetSoftMinVcn 0x19
+#define PPSMC_MSG_EnablePostCode 0x1A
+#define PPSMC_MSG_GetGfxclkFrequency 0x1B
+#define PPSMC_MSG_GetFclkFrequency 0x1C
+#define PPSMC_MSG_AllowGfxOff 0x1D
+#define PPSMC_MSG_DisallowGfxOff 0x1E
+#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
+#define PPSMC_MSG_SetHardMinGfxClk 0x20
+#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
+#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
+#define PPSMC_MSG_SetSoftMaxVcn 0x23
+#define PPSMC_MSG_spare2 0x24
+#define PPSMC_MSG_SetPowerLimitPercentage 0x25
+#define PPSMC_MSG_PowerDownJpeg 0x26
+#define PPSMC_MSG_PowerUpJpeg 0x27
+#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
+#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
+#define PPSMC_MSG_PowerUpCvip 0x2A
+#define PPSMC_MSG_PowerDownCvip 0x2B
+#define PPSMC_MSG_GetPptLimit 0x2C
+#define PPSMC_MSG_GetThermalLimit 0x2D
+#define PPSMC_MSG_GetCurrentTemperature 0x2E
+#define PPSMC_MSG_GetCurrentPower 0x2F
+#define PPSMC_MSG_GetCurrentVoltage 0x30
+#define PPSMC_MSG_GetCurrentCurrent 0x31
+#define PPSMC_MSG_GetAverageCpuActivity 0x32
+#define PPSMC_MSG_GetAverageGfxActivity 0x33
+#define PPSMC_MSG_GetAveragePower 0x34
+#define PPSMC_MSG_GetAverageTemperature 0x35
+#define PPSMC_MSG_SetAveragePowerTimeConstant 0x36
+#define PPSMC_MSG_SetAverageActivityTimeConstant 0x37
+#define PPSMC_MSG_SetAverageTemperatureTimeConstant 0x38
+#define PPSMC_MSG_SetMitigationEndHysteresis 0x39
+#define PPSMC_MSG_GetCurrentFreq 0x3A
+#define PPSMC_MSG_SetReducedPptLimit 0x3B
+#define PPSMC_MSG_SetReducedThermalLimit 0x3C
+#define PPSMC_MSG_DramLogSetDramAddr 0x3D
+#define PPSMC_MSG_StartDramLogging 0x3E
+#define PPSMC_MSG_StopDramLogging 0x3F
+#define PPSMC_MSG_SetSoftMinCclk 0x40
+#define PPSMC_MSG_SetSoftMaxCclk 0x41
+#define PPSMC_Message_Count 0x42
//Argument for PPSMC_MSG_GpuChangeState
enum {
- GpuChangeState_D0Entry = 1,
- GpuChangeState_D3Entry,
+ MODE1_RESET = 1,
+ MODE2_RESET = 2
};
#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware header for vangogh
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 03/10] drm/amd/pm: add new smc message mapping " Xiaojian Du
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to update the smu v11.5 firmware header for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
index abf13abd3919..99a406984135 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_pmfw.h
@@ -89,7 +89,7 @@
#define FEATURE_SOC_VOLTAGE_MON_BIT 55
#define FEATURE_ATHUB_PG_BIT 56
#define FEATURE_ECO_DEEPCSTATE_BIT 57
-#define FEATURE_CC6 58
+#define FEATURE_CC6_BIT 58
#define NUM_FEATURES 59
typedef struct {
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 03/10] drm/amd/pm: add new smc message mapping for vangogh
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware " Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily Xiaojian Du
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to add new smc message mapping for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index c8eee2a427d0..1e8558da84af 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -184,6 +184,30 @@
__SMU_DUMMY_MAP(SetSoftMinSocclkByFreq), \
__SMU_DUMMY_MAP(PowerUpCvip), \
__SMU_DUMMY_MAP(PowerDownCvip), \
+ __SMU_DUMMY_MAP(EnableGfxOff), \
+ __SMU_DUMMY_MAP(SetSoftMinGfxclk), \
+ __SMU_DUMMY_MAP(SetSoftMinFclk), \
+ __SMU_DUMMY_MAP(GetThermalLimit), \
+ __SMU_DUMMY_MAP(GetCurrentTemperature), \
+ __SMU_DUMMY_MAP(GetCurrentPower), \
+ __SMU_DUMMY_MAP(GetCurrentVoltage), \
+ __SMU_DUMMY_MAP(GetCurrentCurrent), \
+ __SMU_DUMMY_MAP(GetAverageCpuActivity), \
+ __SMU_DUMMY_MAP(GetAverageGfxActivity), \
+ __SMU_DUMMY_MAP(GetAveragePower), \
+ __SMU_DUMMY_MAP(GetAverageTemperature), \
+ __SMU_DUMMY_MAP(SetAveragePowerTimeConstant), \
+ __SMU_DUMMY_MAP(SetAverageActivityTimeConstant), \
+ __SMU_DUMMY_MAP(SetAverageTemperatureTimeConstant), \
+ __SMU_DUMMY_MAP(SetMitigationEndHysteresis), \
+ __SMU_DUMMY_MAP(GetCurrentFreq), \
+ __SMU_DUMMY_MAP(SetReducedPptLimit), \
+ __SMU_DUMMY_MAP(SetReducedThermalLimit), \
+ __SMU_DUMMY_MAP(DramLogSetDramAddr), \
+ __SMU_DUMMY_MAP(StartDramLogging), \
+ __SMU_DUMMY_MAP(StopDramLogging), \
+ __SMU_DUMMY_MAP(SetSoftMinCclk), \
+ __SMU_DUMMY_MAP(SetSoftMaxCclk), \
__SMU_DUMMY_MAP(SetGpoFeaturePMask), \
#undef __SMU_DUMMY_MAP
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware " Xiaojian Du
2020-10-27 9:41 ` [PATCH 03/10] drm/amd/pm: add new smc message mapping " Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh Xiaojian Du
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to add UMD Pstate Msg Parameters for vangogh temporarily,
the values refer to renoir.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
index d8696e2274c4..8756766296cd 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h
@@ -27,4 +27,9 @@
extern void vangogh_set_ppt_funcs(struct smu_context *smu);
+/* UMD PState Vangogh Msg Parameters in MHz */
+#define VANGOGH_UMD_PSTATE_GFXCLK 700
+#define VANGOGH_UMD_PSTATE_SOCCLK 678
+#define VANGOGH_UMD_PSTATE_FCLK 800
+
#endif
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (2 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero Xiaojian Du
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to update the smu v11.5 driver interface header for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/pm/inc/smu11_driver_if_vangogh.h | 70 +++++++++----------
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h | 2 +-
2 files changed, 36 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
index 20f8c6f460b8..8f438c80132e 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu11_driver_if_vangogh.h
@@ -100,13 +100,13 @@ typedef struct {
DpmActivityMonitorCoeffExt_t DpmActivityMonitorCoeff[CUSTOM_DPM_SETTING_COUNT];
} CustomDpmSettings_t;
-#define NUM_DCFCLK_DPM_LEVELS 6
-#define NUM_DISPCLK_DPM_LEVELS 6
-#define NUM_DPPCLK_DPM_LEVELS 6
-#define NUM_SOCCLK_DPM_LEVELS 8
-#define NUM_ISPICLK_DPM_LEVELS 6
-#define NUM_ISPXCLK_DPM_LEVELS 6
-#define NUM_VCN_DPM_LEVELS 8
+#define NUM_DCFCLK_DPM_LEVELS 7
+#define NUM_DISPCLK_DPM_LEVELS 7
+#define NUM_DPPCLK_DPM_LEVELS 7
+#define NUM_SOCCLK_DPM_LEVELS 7
+#define NUM_ISPICLK_DPM_LEVELS 7
+#define NUM_ISPXCLK_DPM_LEVELS 7
+#define NUM_VCN_DPM_LEVELS 5
#define NUM_FCLK_DPM_LEVELS 4
#define NUM_SOC_VOLTAGE_LEVELS 8
@@ -160,30 +160,30 @@ typedef struct {
#define THROTTLER_STATUS_BIT_TDC_CVIP 10
typedef struct {
- uint16_t AverageGfxclkFrequency; //[MHz]
- uint16_t AverageSocclkFrequency; //[MHz]
- uint16_t AverageVclkFrequency; //[MHz]
- uint16_t AverageDclkFrequency; //[MHz]
- uint16_t AverageMemclkFrequency; //[MHz]
+ uint16_t GfxclkFrequency; //[MHz]
+ uint16_t SocclkFrequency; //[MHz]
+ uint16_t VclkFrequency; //[MHz]
+ uint16_t DclkFrequency; //[MHz]
+ uint16_t MemclkFrequency; //[MHz]
uint16_t spare;
- uint16_t AverageGfxActivity; //[centi]
- uint16_t AverageUvdActivity; //[centi]
+ uint16_t GfxActivity; //[centi]
+ uint16_t UvdActivity; //[centi]
- uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
- uint16_t CurrentSocketPower; //[mW]
+ uint16_t Voltage[3]; //[mV] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+ uint16_t Current[3]; //[mA] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+ uint16_t Power[3]; //[mW] indices: VDDCR_VDD, VDDCR_SOC, VDDCR_GFX
+ uint16_t CurrentSocketPower; //[mW]
- //3rd party tools in Windows need this info in the case of APUs
- uint16_t CoreFrequency[8]; //[MHz]
- uint16_t CorePower[8]; //[mW]
- uint16_t CoreTemperature[8]; //[centi-Celsius]
- uint16_t L3Frequency[2]; //[MHz]
- uint16_t L3Temperature[2]; //[centi-Celsius]
+ //3rd party tools in Windows need info in the case of APUs
+ uint16_t CoreFrequency[8]; //[MHz]
+ uint16_t CorePower[8]; //[mW]
+ uint16_t CoreTemperature[8]; //[centi-Celsius]
+ uint16_t L3Frequency[2]; //[MHz]
+ uint16_t L3Temperature[2]; //[centi-Celsius]
- uint16_t GfxTemperature; //[centi-Celsius]
- uint16_t SocTemperature; //[centi-Celsius]
+ uint16_t GfxTemperature; //[centi-Celsius]
+ uint16_t SocTemperature; //[centi-Celsius]
uint16_t EdgeTemperature;
uint16_t ThrottlerStatus;
} SmuMetrics_t;
@@ -197,15 +197,15 @@ typedef struct {
#define WORKLOAD_PPLIB_CUSTOM_BIT 5
#define WORKLOAD_PPLIB_COUNT 6
-#define TABLE_BIOS_IF 0 // Called by BIOS
-#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
-#define TABLE_CUSTOM_DPM 2 // Called by Driver
-#define TABLE_SPARE1 3
-#define TABLE_DPMCLOCKS 4 // Called by Driver
-#define TABLE_MOMENTARY_PM 5 // Called by Tools
-#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
-#define TABLE_SMU_METRICS 7 // Called by Driver
-#define TABLE_COUNT 8
+#define TABLE_BIOS_IF 0 // Called by BIOS
+#define TABLE_WATERMARKS 1 // Called by DAL through VBIOS
+#define TABLE_CUSTOM_DPM 2 // Called by Driver
+#define TABLE_SPARE1 3
+#define TABLE_DPMCLOCKS 4 // Called by Driver
+#define TABLE_SPARE2 5 // Called by Tools
+#define TABLE_MODERN_STDBY 6 // Called by Tools for Modern Standby Log
+#define TABLE_SMU_METRICS 7 // Called by Driver
+#define TABLE_COUNT 8
//ISP tile definitions
typedef enum {
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
index b5f0cc7829f0..2efa0dd3719f 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
@@ -32,7 +32,7 @@
#define SMU11_DRIVER_IF_VERSION_NV14 0x36
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3A
#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x5
-#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x01
+#define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
#define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0x9
/* MP Apertures */
--
2.17.1
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* [PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (3 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh Xiaojian Du
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to set the initial value of pm info to zero.
The "value64" is ported to the hwmon and debugfs node, it is a uint64 type.
When it is used for NV10/VEGA10/VEGA20, its word size is appropriate,
because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to high 32bit and low 32bit.
But some asic has only 32bit smu feature mask,and this 32bit mask will fill the low 32bit of "value64".
So if this "value64" is not initialized to zero, the high 32bit will be
filled by a meaningless value, when the whole "value64" is ported to the
"SMC Feature Mask" in the "amdgpu_pm_info" on some specific asic, it
will be a wrong value.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 89632ee88ae2..080af05724ed 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -3464,7 +3464,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
{
uint32_t value;
- uint64_t value64;
+ uint64_t value64 = 0;
uint32_t query = 0;
int size;
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (4 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask " Xiaojian Du
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to remove some redundant smu message mapping for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/inc/smu_types.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/inc/smu_types.h b/drivers/gpu/drm/amd/pm/inc/smu_types.h
index 1e8558da84af..4a6d1381df16 100644
--- a/drivers/gpu/drm/amd/pm/inc/smu_types.h
+++ b/drivers/gpu/drm/amd/pm/inc/smu_types.h
@@ -302,13 +302,9 @@ enum smu_clk_type {
__SMU_DUMMY_MAP(CCLK_DPM), \
__SMU_DUMMY_MAP(FAN_CONTROLLER), \
__SMU_DUMMY_MAP(VCN_DPM), \
- __SMU_DUMMY_MAP(FCLK_DPM), \
- __SMU_DUMMY_MAP(SOCCLK_DPM), \
- __SMU_DUMMY_MAP(MP0CLK_DPM), \
__SMU_DUMMY_MAP(LCLK_DPM), \
__SMU_DUMMY_MAP(SHUBCLK_DPM), \
__SMU_DUMMY_MAP(DCFCLK_DPM), \
- __SMU_DUMMY_MAP(GFX_DPM), \
__SMU_DUMMY_MAP(DS_DCFCLK), \
__SMU_DUMMY_MAP(S0I2), \
__SMU_DUMMY_MAP(SMU_LOW_POWER), \
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask for vangogh
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (5 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 09/10] drm/amd/pm: add some swSMU functions " Xiaojian Du
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to add one new function to get 32 bit feature mask for
vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 55 +++++++++++++++++++++++---
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h | 4 ++
2 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
index 92b2ea4c197b..dc28f22aeb38 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
@@ -346,6 +346,43 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
return ret;
}
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num)
+{
+ uint32_t feature_mask_en_low = 0;
+ uint32_t feature_mask_en_high = 0;
+ struct smu_feature *feature = &smu->smu_feature;
+ int ret = 0;
+
+ if (!feature_mask || num < 2)
+ return -EINVAL;
+
+ if (bitmap_empty(feature->enabled, feature->feature_num)) {
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 0,
+ &feature_mask_en_low);
+
+ if (ret)
+ return ret;
+
+ ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetEnabledSmuFeatures, 1,
+ &feature_mask_en_high);
+
+ if (ret)
+ return ret;
+
+ feature_mask[0] = feature_mask_en_low;
+ feature_mask[1] = feature_mask_en_high;
+
+ } else {
+ bitmap_copy((unsigned long *)feature_mask, feature->enabled,
+ feature->feature_num);
+ }
+
+ return ret;
+
+}
+
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled)
@@ -437,11 +474,19 @@ size_t smu_cmn_get_pp_feature_mask(struct smu_context *smu,
size_t size = 0;
int ret = 0, i;
- ret = smu_cmn_get_enabled_mask(smu,
- feature_mask,
- 2);
- if (ret)
- return 0;
+ if (!smu->is_apu) {
+ ret = smu_cmn_get_enabled_mask(smu,
+ feature_mask,
+ 2);
+ if (ret)
+ return 0;
+ } else {
+ ret = smu_cmn_get_enabled_32_bits_mask(smu,
+ feature_mask,
+ 2);
+ if (ret)
+ return 0;
+ }
size = sprintf(buf + size, "features high: 0x%08x low: 0x%08x\n",
feature_mask[1], feature_mask[0]);
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
index ab577be23c15..01e825d83d8d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.h
@@ -52,6 +52,10 @@ int smu_cmn_get_enabled_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num);
+int smu_cmn_get_enabled_32_bits_mask(struct smu_context *smu,
+ uint32_t *feature_mask,
+ uint32_t num);
+
int smu_cmn_feature_update_enable_state(struct smu_context *smu,
uint64_t feature_mask,
bool enabled);
--
2.17.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 09/10] drm/amd/pm: add some swSMU functions for vangogh.
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (6 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask " Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-27 9:41 ` [PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU " Xiaojian Du
2020-10-28 7:21 ` [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header " Huang Rui
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to add some swSMU functions for vangogh, to support the
sensor info on "hwmon" and pm info.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 411 ++++++++++++++----
1 file changed, 338 insertions(+), 73 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
index 145712a24b80..83a1b0a04eb1 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
@@ -52,53 +52,72 @@
FEATURE_MASK(FEATURE_LCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT) | \
FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
- FEATURE_MASK(FEATURE_GFX_DPM_BIT)| \
- FEATURE_MASK(FEATURE_ISP_DPM_BIT)| \
- FEATURE_MASK(FEATURE_A55_DPM_BIT)| \
- FEATURE_MASK(FEATURE_CVIP_DSP_DPM_BIT))
+ FEATURE_MASK(FEATURE_GFX_DPM_BIT))
static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
- MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
- MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
- MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
- MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
- MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
- MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
- MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
- MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
- MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
- MSG_MAP(Spare, PPSMC_MSG_spare, 1),
- MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
- MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
- MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
- MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 1),
- MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 1),
- MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
- MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
- MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
- MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
- MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
- MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 1),
- MSG_MAP(Spare1, PPSMC_MSG_spare1, 1),
- MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
- MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
- MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
- MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
- MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
- MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
- MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
- MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
- MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
- MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
- MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
- MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
- MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
- MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
- MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
- MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
- MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 1),
- MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 1),
- MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 1),
+ MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
+ MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
+ MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
+ MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
+ MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 0),
+ MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
+ MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
+ MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
+ MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
+ MSG_MAP(Spare, PPSMC_MSG_spare, 0),
+ MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
+ MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
+ MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
+ MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
+ MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
+ MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
+ MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
+ MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
+ MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
+ MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
+ MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
+ MSG_MAP(Spare1, PPSMC_MSG_spare1, 0),
+ MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
+ MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
+ MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
+ MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
+ MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
+ MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
+ MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
+ MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
+ MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
+ MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
+ MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
+ MSG_MAP(Spare2, PPSMC_MSG_spare2, 0),
+ MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
+ MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
+ MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
+ MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
+ MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
+ MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
+ MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
+ MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
+ MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
+ MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
+ MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
+ MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
+ MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
+ MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
+ MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
+ MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
+ MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
+ MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
+ MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
+ MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
+ MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
+ MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
+ MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
+ MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
+ MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
+ MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
+ MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
+ MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
+ MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
};
static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
@@ -116,13 +135,9 @@ static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
FEA_MAP(FAN_CONTROLLER),
FEA_MAP(ULV),
FEA_MAP(VCN_DPM),
- FEA_MAP(FCLK_DPM),
- FEA_MAP(SOCCLK_DPM),
- FEA_MAP(MP0CLK_DPM),
FEA_MAP(LCLK_DPM),
FEA_MAP(SHUBCLK_DPM),
FEA_MAP(DCFCLK_DPM),
- FEA_MAP(GFX_DPM),
FEA_MAP(DS_DCFCLK),
FEA_MAP(S0I2),
FEA_MAP(SMU_LOW_POWER),
@@ -195,6 +210,65 @@ static int vangogh_tables_init(struct smu_context *smu)
return -ENOMEM;
}
+static int vangogh_get_smu_metrics_data(struct smu_context *smu,
+ MetricsMember_t member,
+ uint32_t *value)
+{
+ struct smu_table_context *smu_table = &smu->smu_table;
+
+ SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
+ int ret = 0;
+
+ mutex_lock(&smu->metrics_lock);
+
+ ret = smu_cmn_get_metrics_table_locked(smu,
+ NULL,
+ false);
+ if (ret) {
+ mutex_unlock(&smu->metrics_lock);
+ return ret;
+ }
+
+ switch (member) {
+ case METRICS_AVERAGE_GFXCLK:
+ *value = metrics->GfxclkFrequency;
+ break;
+ case METRICS_AVERAGE_SOCCLK:
+ *value = metrics->SocclkFrequency;
+ break;
+ case METRICS_AVERAGE_UCLK:
+ *value = metrics->MemclkFrequency;
+ break;
+ case METRICS_AVERAGE_GFXACTIVITY:
+ *value = metrics->GfxActivity / 100;
+ break;
+ case METRICS_AVERAGE_VCNACTIVITY:
+ *value = metrics->UvdActivity;
+ break;
+ case METRICS_AVERAGE_SOCKETPOWER:
+ *value = metrics->CurrentSocketPower;
+ break;
+ case METRICS_TEMPERATURE_EDGE:
+ *value = metrics->GfxTemperature / 100 *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case METRICS_TEMPERATURE_HOTSPOT:
+ *value = metrics->SocTemperature / 100 *
+ SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
+ break;
+ case METRICS_THROTTLER_STATUS:
+ *value = metrics->ThrottlerStatus;
+ break;
+ default:
+ *value = UINT_MAX;
+ break;
+ }
+
+ mutex_unlock(&smu->metrics_lock);
+
+ return ret;
+}
+
static int vangogh_allocate_dpm_context(struct smu_context *smu)
{
struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
@@ -230,13 +304,13 @@ static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
if (enable) {
/* vcn dpm on is a prerequisite for vcn power gate messages */
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
if (ret)
return ret;
}
} else {
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
if (ret)
return ret;
@@ -251,13 +325,13 @@ static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
int ret = 0;
if (enable) {
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
if (ret)
return ret;
}
} else {
- if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
+ if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
if (ret)
return ret;
@@ -267,13 +341,6 @@ static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
return ret;
}
-static int vangogh_set_default_dpm_table(struct smu_context *smu)
-{
- struct smu_table_context *smu_table = &smu->smu_table;
-
- return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
-}
-
static int vangogh_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask,
uint32_t num)
@@ -308,23 +375,217 @@ static int vangogh_get_allowed_feature_mask(struct smu_context *smu,
static bool vangogh_is_dpm_running(struct smu_context *smu)
{
- struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+ uint32_t feature_mask[2];
+ uint64_t feature_enabled;
+
+ ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
- /*
- * Until now, the pmfw hasn't exported the interface of SMU
- * feature mask to APU SKU so just force on all the feature
- * at early initial stage.
- */
- if (adev->in_suspend)
+ if (ret)
return false;
- else
- return true;
+ feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
+ ((uint64_t)feature_mask[1] << 32));
+
+ return !!(feature_enabled & SMC_DPM_FEATURE);
+}
+
+static int vangogh_get_current_activity_percent(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ uint32_t *value)
+{
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ ret = vangogh_get_smu_metrics_data(smu,
+ METRICS_AVERAGE_GFXACTIVITY,
+ value);
+ break;
+ default:
+ dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int vangogh_get_gpu_power(struct smu_context *smu, uint32_t *value)
+{
+ if (!value)
+ return -EINVAL;
+
+ return vangogh_get_smu_metrics_data(smu,
+ METRICS_AVERAGE_SOCKETPOWER,
+ value);
+}
+
+static int vangogh_thermal_get_temperature(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ uint32_t *value)
+{
+ int ret = 0;
+
+ if (!value)
+ return -EINVAL;
+
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ ret = vangogh_get_smu_metrics_data(smu,
+ METRICS_TEMPERATURE_HOTSPOT,
+ value);
+ break;
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ ret = vangogh_get_smu_metrics_data(smu,
+ METRICS_TEMPERATURE_EDGE,
+ value);
+ break;
+ default:
+ dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static int vangogh_get_current_clk_freq_by_table(struct smu_context *smu,
+ enum smu_clk_type clk_type,
+ uint32_t *value)
+{
+ MetricsMember_t member_type;
+
+ switch (clk_type) {
+ case SMU_GFXCLK:
+ member_type = METRICS_AVERAGE_GFXCLK;
+ break;
+ case SMU_MCLK:
+ case SMU_UCLK:
+ member_type = METRICS_AVERAGE_UCLK;
+ break;
+ case SMU_SOCCLK:
+ member_type = METRICS_AVERAGE_SOCCLK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return vangogh_get_smu_metrics_data(smu,
+ member_type,
+ value);
+}
+
+static int vangogh_read_sensor(struct smu_context *smu,
+ enum amd_pp_sensors sensor,
+ void *data, uint32_t *size)
+{
+ int ret = 0;
+
+ if (!data || !size)
+ return -EINVAL;
+
+ mutex_lock(&smu->sensor_lock);
+ switch (sensor) {
+ case AMDGPU_PP_SENSOR_GPU_LOAD:
+ ret = vangogh_get_current_activity_percent(smu, sensor, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GPU_POWER:
+ ret = vangogh_get_gpu_power(smu, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_EDGE_TEMP:
+ case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
+ ret = vangogh_thermal_get_temperature(smu, sensor, (uint32_t *)data);
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GFX_MCLK:
+ ret = vangogh_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
+ *(uint32_t *)data *= 100;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_GFX_SCLK:
+ ret = vangogh_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
+ *(uint32_t *)data *= 100;
+ *size = 4;
+ break;
+ case AMDGPU_PP_SENSOR_VDDGFX:
+ ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
+ *size = 4;
+ break;
+ default:
+ ret = -EOPNOTSUPP;
+ break;
+ }
+ mutex_unlock(&smu->sensor_lock);
+
+ return ret;
+}
+
+static int vangogh_set_watermarks_table(struct smu_context *smu,
+ struct pp_smu_wm_range_sets *clock_ranges)
+{
+ int i;
+ int ret = 0;
+ Watermarks_t *table = smu->smu_table.watermarks_table;
+
+ if (!table || !clock_ranges)
+ return -EINVAL;
+
+ if (clock_ranges) {
+ if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
+ clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
+ return -EINVAL;
+
+ for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
+ table->WatermarkRow[WM_DCFCLK][i].MinClock =
+ clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
+ table->WatermarkRow[WM_DCFCLK][i].MaxClock =
+ clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
+ table->WatermarkRow[WM_DCFCLK][i].MinMclk =
+ clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
+ table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
+ clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
+
+ table->WatermarkRow[WM_DCFCLK][i].WmSetting =
+ clock_ranges->reader_wm_sets[i].wm_inst;
+ }
+
+ for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
+ table->WatermarkRow[WM_SOCCLK][i].MinClock =
+ clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
+ table->WatermarkRow[WM_SOCCLK][i].MaxClock =
+ clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
+ table->WatermarkRow[WM_SOCCLK][i].MinMclk =
+ clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
+ table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
+ clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
+
+ table->WatermarkRow[WM_SOCCLK][i].WmSetting =
+ clock_ranges->writer_wm_sets[i].wm_inst;
+ }
+
+ smu->watermarks_bitmap |= WATERMARKS_EXIST;
+ }
+
+ /* pass data to smu controller */
+ if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
+ !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
+ ret = smu_cmn_write_watermarks_table(smu);
+ if (ret) {
+ dev_err(smu->adev->dev, "Failed to update WMTABLE!");
+ return ret;
+ }
+ smu->watermarks_bitmap |= WATERMARKS_LOADED;
+ }
+
+ return 0;
}
static const struct pptable_funcs vangogh_ppt_funcs = {
- .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
- .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
+
.check_fw_status = smu_v11_0_check_fw_status,
.check_fw_version = smu_v11_0_check_fw_version,
.init_smc_tables = vangogh_init_smc_tables,
@@ -336,10 +597,14 @@ static const struct pptable_funcs vangogh_ppt_funcs = {
.notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
.send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
.send_smc_msg = smu_cmn_send_smc_msg,
- .set_default_dpm_table = vangogh_set_default_dpm_table,
+ .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
+ .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
.is_dpm_running = vangogh_is_dpm_running,
+ .read_sensor = vangogh_read_sensor,
+ .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
- .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
+ .set_watermarks_table = vangogh_set_watermarks_table,
+ .set_driver_table_location = smu_v11_0_set_driver_table_location,
.disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
.interrupt_work = smu_v11_0_interrupt_work,
};
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU for vangogh.
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (7 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 09/10] drm/amd/pm: add some swSMU functions " Xiaojian Du
@ 2020-10-27 9:41 ` Xiaojian Du
2020-10-28 7:21 ` [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header " Huang Rui
9 siblings, 0 replies; 11+ messages in thread
From: Xiaojian Du @ 2020-10-27 9:41 UTC (permalink / raw)
To: amd-gfx, ray.huang, evan.quan, Alexander.Deucher, kevin1.wang
Cc: Xiaojian Du, xinmei.huang, prike.liang, changfeng.zhu
This patch is to enable the rest functions of swSMU for vangogh.
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
index 1a8a9cf993ce..39990790ed67 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
@@ -1111,9 +1111,6 @@ static int smu_hw_init(void *handle)
smu_set_gfx_cgpg(&adev->smu, true);
}
- if (adev->asic_type == CHIP_VANGOGH)
- return 0;
-
if (!smu->pm_enabled)
return 0;
--
2.17.1
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
` (8 preceding siblings ...)
2020-10-27 9:41 ` [PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU " Xiaojian Du
@ 2020-10-28 7:21 ` Huang Rui
9 siblings, 0 replies; 11+ messages in thread
From: Huang Rui @ 2020-10-28 7:21 UTC (permalink / raw)
To: Du, Xiaojian
Cc: Wang, Kevin(Yang),
Liang, Prike, amd-gfx, Huang, Shimmer, Zhu, Changfeng, Deucher,
Alexander, Quan, Evan
On Tue, Oct 27, 2020 at 05:41:24PM +0800, Du, Xiaojian wrote:
> This patch is to update the smu v11.5 smc header for vangogh.
>
> Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
> Reviewed-by: Huang Rui <ray.huang@amd.com>
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h | 114 +++++++++++--------
> 1 file changed, 68 insertions(+), 46 deletions(-)
Series are Reviewed-by: Huang Rui <ray.huang@amd.com>
>
> diff --git a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
> index 55c1b151a68d..1ada0eb64663 100644
> --- a/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
> +++ b/drivers/gpu/drm/amd/pm/inc/smu_v11_5_ppsmc.h
> @@ -32,55 +32,77 @@
> #define PPSMC_Result_CmdRejectedBusy 0xFC
>
> // Message Definitions:
> -#define PPSMC_MSG_TestMessage 0x1
> -#define PPSMC_MSG_GetSmuVersion 0x2
> -#define PPSMC_MSG_GetDriverIfVersion 0x3
> -#define PPSMC_MSG_EnableGfxOff 0x4
> -#define PPSMC_MSG_DisableGfxOff 0x5
> -#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
> -#define PPSMC_MSG_PowerUpIspByTile 0x7
> -#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
> -#define PPSMC_MSG_PowerUpVcn 0x9
> -#define PPSMC_MSG_spare 0xA
> -#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
> -#define PPSMC_MSG_SetMinVideoGfxclkFreq 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
> -#define PPSMC_MSG_ActiveProcessNotify 0xD
> -#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
> -#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
> -#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
> -#define PPSMC_MSG_SetDriverDramAddrLow 0x11
> -#define PPSMC_MSG_TransferTableSmu2Dram 0x12
> -#define PPSMC_MSG_TransferTableDram2Smu 0x13
> -#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
> -#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
> -#define PPSMC_MSG_spare1 0x16
> -#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
> -#define PPSMC_MSG_SetMinVideoFclkFreq 0x18
> -#define PPSMC_MSG_SetSoftMinVcn 0x19
> -#define PPSMC_MSG_EnablePostCode 0x1A
> -#define PPSMC_MSG_GetGfxclkFrequency 0x1B
> -#define PPSMC_MSG_GetFclkFrequency 0x1C
> -#define PPSMC_MSG_AllowGfxOff 0x1D
> -#define PPSMC_MSG_DisallowGfxOff 0x1E
> -#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
> -#define PPSMC_MSG_SetHardMinGfxClk 0x20
> -#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
> -#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
> -#define PPSMC_MSG_SetSoftMaxVcn 0x23
> -#define PPSMC_MSG_GpuChangeState 0x24 //FIXME AHOLLA - check how to do for VGM
> -#define PPSMC_MSG_SetPowerLimitPercentage 0x25
> -#define PPSMC_MSG_PowerDownJpeg 0x26
> -#define PPSMC_MSG_PowerUpJpeg 0x27
> -#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
> -#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
> -#define PPSMC_MSG_PowerUpCvip 0x2A
> -#define PPSMC_MSG_PowerDownCvip 0x2B
> -#define PPSMC_Message_Count 0x2C
> +#define PPSMC_MSG_TestMessage 0x1
> +#define PPSMC_MSG_GetSmuVersion 0x2
> +#define PPSMC_MSG_GetDriverIfVersion 0x3
> +#define PPSMC_MSG_EnableGfxOff 0x4
> +#define PPSMC_MSG_DisableGfxOff 0x5
> +#define PPSMC_MSG_PowerDownIspByTile 0x6 // ISP is power gated by default
> +#define PPSMC_MSG_PowerUpIspByTile 0x7
> +#define PPSMC_MSG_PowerDownVcn 0x8 // VCN is power gated by default
> +#define PPSMC_MSG_PowerUpVcn 0x9
> +#define PPSMC_MSG_spare 0xA
> +#define PPSMC_MSG_SetHardMinVcn 0xB // For wireless display
> +#define PPSMC_MSG_SetSoftMinGfxclk 0xC //Sets SoftMin for GFXCLK. Arg is in MHz
> +#define PPSMC_MSG_ActiveProcessNotify 0xD
> +#define PPSMC_MSG_SetHardMinIspiclkByFreq 0xE
> +#define PPSMC_MSG_SetHardMinIspxclkByFreq 0xF
> +#define PPSMC_MSG_SetDriverDramAddrHigh 0x10
> +#define PPSMC_MSG_SetDriverDramAddrLow 0x11
> +#define PPSMC_MSG_TransferTableSmu2Dram 0x12
> +#define PPSMC_MSG_TransferTableDram2Smu 0x13
> +#define PPSMC_MSG_GfxDeviceDriverReset 0x14 //mode 2 reset during TDR
> +#define PPSMC_MSG_GetEnabledSmuFeatures 0x15
> +#define PPSMC_MSG_spare1 0x16
> +#define PPSMC_MSG_SetHardMinSocclkByFreq 0x17
> +#define PPSMC_MSG_SetSoftMinFclk 0x18 //Used to be PPSMC_MSG_SetMinVideoFclkFreq
> +#define PPSMC_MSG_SetSoftMinVcn 0x19
> +#define PPSMC_MSG_EnablePostCode 0x1A
> +#define PPSMC_MSG_GetGfxclkFrequency 0x1B
> +#define PPSMC_MSG_GetFclkFrequency 0x1C
> +#define PPSMC_MSG_AllowGfxOff 0x1D
> +#define PPSMC_MSG_DisallowGfxOff 0x1E
> +#define PPSMC_MSG_SetSoftMaxGfxClk 0x1F
> +#define PPSMC_MSG_SetHardMinGfxClk 0x20
> +#define PPSMC_MSG_SetSoftMaxSocclkByFreq 0x21
> +#define PPSMC_MSG_SetSoftMaxFclkByFreq 0x22
> +#define PPSMC_MSG_SetSoftMaxVcn 0x23
> +#define PPSMC_MSG_spare2 0x24
> +#define PPSMC_MSG_SetPowerLimitPercentage 0x25
> +#define PPSMC_MSG_PowerDownJpeg 0x26
> +#define PPSMC_MSG_PowerUpJpeg 0x27
> +#define PPSMC_MSG_SetHardMinFclkByFreq 0x28
> +#define PPSMC_MSG_SetSoftMinSocclkByFreq 0x29
> +#define PPSMC_MSG_PowerUpCvip 0x2A
> +#define PPSMC_MSG_PowerDownCvip 0x2B
> +#define PPSMC_MSG_GetPptLimit 0x2C
> +#define PPSMC_MSG_GetThermalLimit 0x2D
> +#define PPSMC_MSG_GetCurrentTemperature 0x2E
> +#define PPSMC_MSG_GetCurrentPower 0x2F
> +#define PPSMC_MSG_GetCurrentVoltage 0x30
> +#define PPSMC_MSG_GetCurrentCurrent 0x31
> +#define PPSMC_MSG_GetAverageCpuActivity 0x32
> +#define PPSMC_MSG_GetAverageGfxActivity 0x33
> +#define PPSMC_MSG_GetAveragePower 0x34
> +#define PPSMC_MSG_GetAverageTemperature 0x35
> +#define PPSMC_MSG_SetAveragePowerTimeConstant 0x36
> +#define PPSMC_MSG_SetAverageActivityTimeConstant 0x37
> +#define PPSMC_MSG_SetAverageTemperatureTimeConstant 0x38
> +#define PPSMC_MSG_SetMitigationEndHysteresis 0x39
> +#define PPSMC_MSG_GetCurrentFreq 0x3A
> +#define PPSMC_MSG_SetReducedPptLimit 0x3B
> +#define PPSMC_MSG_SetReducedThermalLimit 0x3C
> +#define PPSMC_MSG_DramLogSetDramAddr 0x3D
> +#define PPSMC_MSG_StartDramLogging 0x3E
> +#define PPSMC_MSG_StopDramLogging 0x3F
> +#define PPSMC_MSG_SetSoftMinCclk 0x40
> +#define PPSMC_MSG_SetSoftMaxCclk 0x41
> +#define PPSMC_Message_Count 0x42
>
> //Argument for PPSMC_MSG_GpuChangeState
> enum {
> - GpuChangeState_D0Entry = 1,
> - GpuChangeState_D3Entry,
> + MODE1_RESET = 1,
> + MODE2_RESET = 2
> };
>
> #endif
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-10-28 7:21 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-10-27 9:41 [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 02/10] drm/amd/pm: update the smu v11.5 firmware " Xiaojian Du
2020-10-27 9:41 ` [PATCH 03/10] drm/amd/pm: add new smc message mapping " Xiaojian Du
2020-10-27 9:41 ` [PATCH 04/10] drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarily Xiaojian Du
2020-10-27 9:41 ` [PATCH 05/10] drm/amd/pm: update the smu v11.5 driver interface header for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 06/10] drm/amd/pm: set the initial value of pm info to zero Xiaojian Du
2020-10-27 9:41 ` [PATCH 07/10] drm/amd/pm: remove some redundant smu message mapping for vangogh Xiaojian Du
2020-10-27 9:41 ` [PATCH 08/10] drm/amd/pm: add one new function to get 32 bit feature mask " Xiaojian Du
2020-10-27 9:41 ` [PATCH 09/10] drm/amd/pm: add some swSMU functions " Xiaojian Du
2020-10-27 9:41 ` [PATCH 10/10] drm/amd/pm: enable the rest functions of swSMU " Xiaojian Du
2020-10-28 7:21 ` [PATCH 01/10] drm/amd/pm: update the smu v11.5 smc header " Huang Rui
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