From: Peng Ju Zhou <PengJu.Zhou@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Victor <Victor.Zhao@amd.com>
Subject: [PATCH 8/8] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
Date: Thu, 8 Apr 2021 18:22:05 +0800 [thread overview]
Message-ID: <20210408102205.911-8-PengJu.Zhou@amd.com> (raw)
In-Reply-To: <20210408102205.911-1-PengJu.Zhou@amd.com>
use psp to program IH_RB_CNTL* if indirect access
for ih enabled in SRIOV environment.
Signed-off-by: Victor <Victor.Zhao@amd.com>
Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
---
drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 19 +++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/nv.c | 2 +-
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index f4e4040bbd25..903772b37759 100644
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -151,7 +151,14 @@ static int navi10_ih_toggle_ring_interrupts(struct amdgpu_device *adev,
/* enable_intr field is only valid in ring0 */
if (ih == &adev->irq.ih)
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
- WREG32(ih_regs->ih_rb_cntl, tmp);
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (enable) {
ih->enabled = true;
@@ -261,7 +268,15 @@ static int navi10_ih_enable_ring(struct amdgpu_device *adev,
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
}
- WREG32(ih_regs->ih_rb_cntl, tmp);
+
+ if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
+ if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL, tmp)) {
+ DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ WREG32(ih_regs->ih_rb_cntl, tmp);
+ }
if (ih == &adev->irq.ih) {
/* set the ih ring 0 writeback address whether it's enabled or not */
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index c848b9470f66..0fc30afb4d61 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -738,8 +738,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
case CHIP_NAVI12:
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block);
- amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+ amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
--
2.17.1
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next prev parent reply other threads:[~2021-04-08 10:22 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-08 10:21 [PATCH 1/8] drm/amdgpu: change MMHUB register access from MMIO to RLCG Peng Ju Zhou
2021-04-08 10:21 ` [PATCH 2/8] drm/amdgpu: Change GC(KFD/GFX) " Peng Ju Zhou
2021-04-08 10:22 ` [PATCH 3/8] drm/amdgpu: Change GC(SDMA) " Peng Ju Zhou
2021-04-08 10:22 ` [PATCH 4/8] drm/amdgpu: Change GC(GFX/GFXHUB) " Peng Ju Zhou
2021-04-08 10:22 ` [PATCH 5/8] drm/amdgpu: Change GC(GMC/GFXHUB/..) " Peng Ju Zhou
2021-04-08 10:22 ` [PATCH 6/8] drm/amdgpu: Change GC(GFXHUB) " Peng Ju Zhou
2021-04-08 10:22 ` [PATCH 7/8] drm/amdgpu: Change GC(GFX) " Peng Ju Zhou
2021-04-08 10:22 ` Peng Ju Zhou [this message]
2021-04-08 14:58 ` [PATCH 1/8] drm/amdgpu: change MMHUB " Felix Kuehling
2021-04-09 3:35 ` Zhou, Peng Ju
2021-04-15 7:25 ` Zhou, Peng Ju
2021-04-15 15:47 ` Felix Kuehling
2021-04-16 3:18 ` Zhou, Peng Ju
-- strict thread matches above, loose matches on Subject: below --
2021-04-08 5:32 Peng Ju Zhou
2021-04-08 5:32 ` [PATCH 8/8] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers Peng Ju Zhou
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