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Signed-off-by: Alex Deucher --- .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 50 +++++++++---------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c index ae11f5ed7a97..d96f904a765b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c @@ -345,7 +345,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, /* DPM UCLK enablement should be skipped for navi10 A0 secure board */ if (!(is_asic_secure(smu) && - (adev->asic_type == CHIP_NAVI10) && + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) && (adev->pm.pp_feature & PP_MCLK_DPM_MASK)) *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT) @@ -354,7 +354,7 @@ navi10_get_allowed_feature_mask(struct smu_context *smu, /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */ if (is_asic_secure(smu) && - (adev->asic_type == CHIP_NAVI10) && + (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (adev->rev_id == 0)) *(uint64_t *)feature_mask &= ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT); @@ -925,18 +925,18 @@ static int navi1x_get_smu_metrics_data(struct smu_context *smu, return ret; } - switch (adev->asic_type) { - case CHIP_NAVI12: + switch (adev->ip_versions[MP1_HWIP]) { + case IP_VERSION(11, 0, 9): if (smu_version > 0x00341C00) ret = navi12_get_smu_metrics_data(smu, member, value); else ret = navi12_get_legacy_smu_metrics_data(smu, member, value); break; - case CHIP_NAVI10: - case CHIP_NAVI14: + case IP_VERSION(11, 0, 0): + case IP_VERSION(11, 0, 5): default: - if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) || - ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) + if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || + ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) ret = navi10_get_smu_metrics_data(smu, member, value); else ret = navi10_get_legacy_smu_metrics_data(smu, member, value); @@ -1509,8 +1509,8 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) uint32_t sclk_freq; pstate_table->gfxclk_pstate.min = gfx_table->min; - switch (adev->asic_type) { - case CHIP_NAVI10: + switch (adev->ip_versions[MP1_HWIP]) { + case IP_VERSION(11, 0, 0): switch (adev->pdev->revision) { case 0xf0: /* XTX */ case 0xc0: @@ -1525,7 +1525,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) break; } break; - case CHIP_NAVI14: + case IP_VERSION(11, 0, 5): switch (adev->pdev->revision) { case 0xc7: /* XT */ case 0xf4: @@ -1548,7 +1548,7 @@ static int navi10_populate_umd_state_clk(struct smu_context *smu) break; } break; - case CHIP_NAVI12: + case IP_VERSION(11, 0, 9): sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK; break; default: @@ -2562,8 +2562,8 @@ static bool navi10_need_umc_cdr_workaround(struct smu_context *smu) if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) return false; - if (adev->asic_type == CHIP_NAVI10 || - adev->asic_type == CHIP_NAVI14) + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0) || + adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) return true; return false; @@ -2671,8 +2671,8 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu) * - PPSMC_MSG_SetDriverDummyTableDramAddrLow * - PPSMC_MSG_GetUMCFWWA */ - if (((adev->asic_type == CHIP_NAVI10) && (pmfw_version >= 0x2a3500)) || - ((adev->asic_type == CHIP_NAVI14) && (pmfw_version >= 0x351D00))) { + if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) || + ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) { ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GET_UMC_FW_WA, 0, @@ -2691,13 +2691,13 @@ static int navi10_run_umc_cdr_workaround(struct smu_context *smu) return 0; if (umc_fw_disable_cdr) { - if (adev->asic_type == CHIP_NAVI10) + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) return navi10_umc_hybrid_cdr_workaround(smu); } else { return navi10_set_dummy_pstates_table_location(smu); } } else { - if (adev->asic_type == CHIP_NAVI10) + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) return navi10_umc_hybrid_cdr_workaround(smu); } @@ -3151,18 +3151,18 @@ static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu, return ret; } - switch (adev->asic_type) { - case CHIP_NAVI12: + switch (adev->ip_versions[MP1_HWIP]) { + case IP_VERSION(11, 0, 9): if (smu_version > 0x00341C00) ret = navi12_get_gpu_metrics(smu, table); else ret = navi12_get_legacy_gpu_metrics(smu, table); break; - case CHIP_NAVI10: - case CHIP_NAVI14: + case IP_VERSION(11, 0, 0): + case IP_VERSION(11, 0, 5): default: - if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) || - ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) + if (((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || + ((adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) ret = navi10_get_gpu_metrics(smu, table); else ret =navi10_get_legacy_gpu_metrics(smu, table); @@ -3180,7 +3180,7 @@ static int navi10_enable_mgpu_fan_boost(struct smu_context *smu) uint32_t param = 0; /* Navi12 does not support this */ - if (adev->asic_type == CHIP_NAVI12) + if (adev->ip_versions[MP1_HWIP] == IP_VERSION(11, 0, 9)) return 0; /* -- 2.31.1