* [PATCH 1/4] drm/amd/psp: Add C2P registers to mp_13_0_2 header
@ 2022-05-05 20:05 Alex Deucher
2022-05-05 20:05 ` [PATCH 2/4] drm/amdgpu/psp: Add VBIOS flash handler Alex Deucher
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-05 20:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Andrey Grodzovsky, Hawking Zhang
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../include/asic_reg/mp/mp_13_0_2_offset.h | 48 +++++++++++++
.../include/asic_reg/mp/mp_13_0_2_sh_mask.h | 72 +++++++++++++++++++
2 files changed, 120 insertions(+)
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h
index 0b1e781fed7e..f6c0e2d2cee3 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_offset.h
@@ -172,6 +172,54 @@
#define regMP0_SMN_C2PMSG_102_BASE_IDX 0
#define regMP0_SMN_C2PMSG_103 0x00a7
#define regMP0_SMN_C2PMSG_103_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_104 0x00a8
+#define regMP0_SMN_C2PMSG_104_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_105 0x00a9
+#define regMP0_SMN_C2PMSG_105_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_106 0x00aa
+#define regMP0_SMN_C2PMSG_106_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_107 0x00ab
+#define regMP0_SMN_C2PMSG_107_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_108 0x00ac
+#define regMP0_SMN_C2PMSG_108_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_109 0x00ad
+#define regMP0_SMN_C2PMSG_109_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_110 0x00ae
+#define regMP0_SMN_C2PMSG_110_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_111 0x00af
+#define regMP0_SMN_C2PMSG_111_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_112 0x00b0
+#define regMP0_SMN_C2PMSG_112_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_113 0x00b1
+#define regMP0_SMN_C2PMSG_113_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_114 0x00b2
+#define regMP0_SMN_C2PMSG_114_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_115 0x00b3
+#define regMP0_SMN_C2PMSG_115_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_116 0x00b4
+#define regMP0_SMN_C2PMSG_116_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_117 0x00b5
+#define regMP0_SMN_C2PMSG_117_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_118 0x00b6
+#define regMP0_SMN_C2PMSG_118_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_119 0x00b7
+#define regMP0_SMN_C2PMSG_119_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_120 0x00b8
+#define regMP0_SMN_C2PMSG_120_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_121 0x00b9
+#define regMP0_SMN_C2PMSG_121_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_122 0x00ba
+#define regMP0_SMN_C2PMSG_122_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_123 0x00bb
+#define regMP0_SMN_C2PMSG_123_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_124 0x00bc
+#define regMP0_SMN_C2PMSG_124_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_125 0x00bd
+#define regMP0_SMN_C2PMSG_125_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_126 0x00be
+#define regMP0_SMN_C2PMSG_126_BASE_IDX 0
+#define regMP0_SMN_C2PMSG_127 0x00bf
+#define regMP0_SMN_C2PMSG_127_BASE_IDX 0
#define regMP0_SMN_IH_CREDIT 0x00c1
#define regMP0_SMN_IH_CREDIT_BASE_IDX 0
#define regMP0_SMN_IH_SW_INT 0x00c2
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h
index 0af8e95dadab..6e29a185de51 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/mp/mp_13_0_2_sh_mask.h
@@ -484,6 +484,78 @@
//MP1_SMN_C2PMSG_103
#define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0
#define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_104
+#define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_105
+#define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_106
+#define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_107
+#define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_108
+#define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_109
+#define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_110
+#define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_111
+#define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_112
+#define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_113
+#define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_114
+#define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_115
+#define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_116
+#define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_117
+#define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_118
+#define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_119
+#define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_120
+#define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_121
+#define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_122
+#define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_123
+#define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_124
+#define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_125
+#define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_126
+#define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL
+//MP1_SMN_C2PMSG_127
+#define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0
+#define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL
//MP1_SMN_IH_CREDIT
#define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0
#define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/4] drm/amdgpu/psp: Add VBIOS flash handler
2022-05-05 20:05 [PATCH 1/4] drm/amd/psp: Add C2P registers to mp_13_0_2 header Alex Deucher
@ 2022-05-05 20:05 ` Alex Deucher
2022-05-05 20:05 ` [PATCH 3/4] drm/amdgpu/psp: Add vbflash sysfs interface support Alex Deucher
2022-05-05 20:05 ` [PATCH 4/4] drm/amdgpu: add sysfs to shows psp vbflash status Alex Deucher
2 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-05 20:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Andrey Grodzovsky, Likun Gao, Hawking Zhang
From: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Add psp vbflash function for psp v13.
v2: fix warnings
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 5 ++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 74 ++++++++++++++++++++++++-
2 files changed, 78 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index a9fe05c38715..81ecbdeb1ddb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -129,6 +129,7 @@ struct psp_funcs
void (*ring_set_wptr)(struct psp_context *psp, uint32_t value);
int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
+ int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
};
#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
@@ -417,6 +418,10 @@ struct amdgpu_psp_funcs {
((psp)->funcs->read_usbc_pd_fw ? \
(psp)->funcs->read_usbc_pd_fw((psp), fw_ver) : -EINVAL)
+#define psp_update_spirom(psp, fw_pri_mc_addr) \
+ ((psp)->funcs->update_spirom ? \
+ (psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
+
extern const struct amd_ip_funcs psp_ip_funcs;
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 9beb94681dd2..894ac0c64bf6 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -50,6 +50,15 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
/* Read USB-PD from LFB */
#define GFX_CMD_USB_PD_USE_LFB 0x480
+/* VBIOS gfl defines */
+#define MBOX_READY_MASK 0x80000000
+#define MBOX_STATUS_MASK 0x0000FFFF
+#define MBOX_COMMAND_MASK 0x00FF0000
+#define MBOX_READY_FLAG 0x80000000
+#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
+#define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
+#define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
+
static int psp_v13_0_init_microcode(struct psp_context *psp)
{
struct amdgpu_device *adev = psp->adev;
@@ -465,6 +474,68 @@ static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
return ret;
}
+static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
+{
+ uint32_t reg_status = 0, reg_val = 0;
+ struct amdgpu_device *adev = psp->adev;
+ int ret;
+
+ /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
+ reg_val |= (cmd << 16);
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
+
+ /* Ring the doorbell */
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
+
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
+ MBOX_READY_FLAG, MBOX_READY_MASK, false);
+ if (ret) {
+ dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
+ return ret;
+ }
+
+ reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
+ if ((reg_status & 0xFFFF) != 0) {
+ dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
+ cmd, reg_status & 0xFFFF);
+ return -EIO;
+ }
+
+ return 0;
+}
+
+int psp_v13_0_update_spirom(struct psp_context *psp, uint64_t fw_pri_mc_addr)
+{
+ struct amdgpu_device *adev = psp->adev;
+ int ret;
+
+ /* Confirm PSP is ready to start */
+ ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
+ MBOX_READY_FLAG, MBOX_READY_MASK, false);
+ if (ret) {
+ dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
+ return ret;
+ }
+
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
+
+ ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
+ if (ret)
+ return ret;
+
+ WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
+
+ ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
+ if (ret)
+ return ret;
+
+ ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
@@ -481,7 +552,8 @@ static const struct psp_funcs psp_v13_0_funcs = {
.ring_get_wptr = psp_v13_0_ring_get_wptr,
.ring_set_wptr = psp_v13_0_ring_set_wptr,
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
- .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw
+ .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
+ .update_spirom = psp_v13_0_update_spirom
};
void psp_v13_0_set_psp_funcs(struct psp_context *psp)
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 3/4] drm/amdgpu/psp: Add vbflash sysfs interface support
2022-05-05 20:05 [PATCH 1/4] drm/amd/psp: Add C2P registers to mp_13_0_2 header Alex Deucher
2022-05-05 20:05 ` [PATCH 2/4] drm/amdgpu/psp: Add VBIOS flash handler Alex Deucher
@ 2022-05-05 20:05 ` Alex Deucher
2022-05-05 20:05 ` [PATCH 4/4] drm/amdgpu: add sysfs to shows psp vbflash status Alex Deucher
2 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-05 20:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Andrey Grodzovsky, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add sysfs interface to copy VBIOS.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 117 +++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6 ++
4 files changed, 134 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 058f272e40ee..3c20c2eadf4e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1013,6 +1013,7 @@ struct amdgpu_device {
bool pm_sysfs_en;
bool ucode_sysfs_en;
+ bool psp_sysfs_en;
/* Chip product information */
char product_number[16];
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b07f295a449e..b583026dc893 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3868,6 +3868,14 @@ int amdgpu_device_init(struct amdgpu_device *adev,
} else
adev->ucode_sysfs_en = true;
+ r = amdgpu_psp_sysfs_init(adev);
+ if (r) {
+ adev->psp_sysfs_en = false;
+ if (!amdgpu_sriov_vf(adev))
+ DRM_ERROR("Creating psp sysfs failed\n");
+ } else
+ adev->psp_sysfs_en = true;
+
/*
* Register gpu instance before amdgpu_device_enable_mgpu_fan_boost.
* Otherwise the mgpu fan boost feature will be skipped due to the
@@ -4000,6 +4008,8 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
amdgpu_pm_sysfs_fini(adev);
if (adev->ucode_sysfs_en)
amdgpu_ucode_sysfs_fini(adev);
+ if (adev->psp_sysfs_en)
+ amdgpu_psp_sysfs_fini(adev);
sysfs_remove_files(&adev->dev->kobj, amdgpu_dev_attributes);
/* disable ras feature must before hw fini */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 25c90ad2c0b7..7d0a37a94ea6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -42,6 +42,8 @@
#include "amdgpu_securedisplay.h"
#include "amdgpu_atomfirmware.h"
+#define AMD_VBIOS_FILE_MAX_SIZE_B (1024*1024*3)
+
static int psp_sysfs_init(struct amdgpu_device *adev);
static void psp_sysfs_fini(struct amdgpu_device *adev);
@@ -3443,6 +3445,116 @@ int is_psp_fw_valid(struct psp_bin_desc bin)
return bin.size_bytes;
}
+static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr,
+ char *buffer, loff_t pos, size_t count)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+
+ /* Safeguard against memory drain */
+ if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
+ dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
+ vfree(adev->psp.vbflash_tmp_buf);
+ adev->psp.vbflash_tmp_buf = NULL;
+ adev->psp.vbflash_image_size = 0;
+ return -ENOMEM;
+ }
+
+ /* TODO Just allocate max for now and optimize to realloc later if needed */
+ if (!adev->psp.vbflash_tmp_buf) {
+ adev->psp.vbflash_tmp_buf = vmalloc(AMD_VBIOS_FILE_MAX_SIZE_B);
+ if (!adev->psp.vbflash_tmp_buf)
+ return -ENOMEM;
+ }
+
+ mutex_lock(&adev->psp.mutex);
+ memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
+ adev->psp.vbflash_image_size += count;
+ mutex_unlock(&adev->psp.mutex);
+
+ dev_info(adev->dev, "VBIOS flash write PSP done");
+
+ return count;
+}
+
+static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
+ struct bin_attribute *bin_attr, char *buffer,
+ loff_t pos, size_t count)
+{
+ struct device *dev = kobj_to_dev(kobj);
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ struct amdgpu_bo *fw_buf_bo = NULL;
+ uint64_t fw_pri_mc_addr;
+ void *fw_pri_cpu_addr;
+ int ret;
+
+ dev_info(adev->dev, "VBIOS flash to PSP started");
+
+ ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
+ AMDGPU_GPU_PAGE_SIZE,
+ AMDGPU_GEM_DOMAIN_VRAM,
+ &fw_buf_bo,
+ &fw_pri_mc_addr,
+ &fw_pri_cpu_addr);
+ if (ret)
+ goto rel_buf;
+
+ memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
+
+ mutex_lock(&adev->psp.mutex);
+ ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
+ mutex_unlock(&adev->psp.mutex);
+
+ amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
+
+rel_buf:
+ vfree(adev->psp.vbflash_tmp_buf);
+ adev->psp.vbflash_tmp_buf = NULL;
+ adev->psp.vbflash_image_size = 0;
+
+ if (ret) {
+ dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
+ return ret;
+ }
+
+ dev_info(adev->dev, "VBIOS flash to PSP done");
+ return 0;
+}
+
+static const struct bin_attribute psp_vbflash_bin_attr = {
+ .attr = {.name = "psp_vbflash", .mode = 0664},
+ .size = 0,
+ .write = amdgpu_psp_vbflash_write,
+ .read = amdgpu_psp_vbflash_read,
+};
+
+int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
+{
+ int ret = 0;
+ struct psp_context *psp = &adev->psp;
+
+ if (amdgpu_sriov_vf(adev))
+ return -EINVAL;
+
+ switch (adev->ip_versions[MP0_HWIP][0]) {
+ case IP_VERSION(13, 0, 0):
+ case IP_VERSION(13, 0, 7):
+ if (!psp->adev) {
+ psp->adev = adev;
+ psp_v13_0_set_psp_funcs(psp);
+ }
+ ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
+ if (ret)
+ dev_err(adev->dev, "Failed to create device file psp_vbflash");
+ return ret;
+ default:
+ return 0;
+ }
+}
+
const struct amd_ip_funcs psp_ip_funcs = {
.name = "psp",
.early_init = psp_early_init,
@@ -3471,6 +3583,11 @@ static int psp_sysfs_init(struct amdgpu_device *adev)
return ret;
}
+void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
+{
+ sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
+}
+
static void psp_sysfs_fini(struct amdgpu_device *adev)
{
device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index 81ecbdeb1ddb..db7b7dbb9c93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -372,6 +372,9 @@ struct psp_context
struct psp_memory_training_context mem_train_ctx;
uint32_t boot_cfg_bitmask;
+
+ char *vbflash_tmp_buf;
+ size_t vbflash_image_size;
};
struct amdgpu_psp_funcs {
@@ -501,4 +504,7 @@ int psp_load_fw_list(struct psp_context *psp,
void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size);
int is_psp_fw_valid(struct psp_bin_desc bin);
+
+int amdgpu_psp_sysfs_init(struct amdgpu_device *adev);
+void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev);
#endif
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 4/4] drm/amdgpu: add sysfs to shows psp vbflash status
2022-05-05 20:05 [PATCH 1/4] drm/amd/psp: Add C2P registers to mp_13_0_2 header Alex Deucher
2022-05-05 20:05 ` [PATCH 2/4] drm/amdgpu/psp: Add VBIOS flash handler Alex Deucher
2022-05-05 20:05 ` [PATCH 3/4] drm/amdgpu/psp: Add vbflash sysfs interface support Alex Deucher
@ 2022-05-05 20:05 ` Alex Deucher
2 siblings, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2022-05-05 20:05 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Hawking Zhang
From: Likun Gao <Likun.Gao@amd.com>
Add new sysfs interface to shows the status of psp vbflash status.
V2: rename the sysfs interface, and set more return value.
(0: not start; 1: in progress; MBX115 value when vbflash finish)
V3: warning fixes
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 25 +++++++++++++++++++++++++
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 6 ++++++
drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 15 ++++++++++++++-
3 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7d0a37a94ea6..1f3f93e9eeb3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -3453,6 +3453,8 @@ static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
struct drm_device *ddev = dev_get_drvdata(dev);
struct amdgpu_device *adev = drm_to_adev(ddev);
+ adev->psp.vbflash_done = false;
+
/* Safeguard against memory drain */
if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
@@ -3524,6 +3526,23 @@ static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
return 0;
}
+static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct drm_device *ddev = dev_get_drvdata(dev);
+ struct amdgpu_device *adev = drm_to_adev(ddev);
+ uint32_t vbflash_status;
+
+ vbflash_status = psp_vbflash_status(&adev->psp);
+ if (!adev->psp.vbflash_done)
+ vbflash_status = 0;
+ else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
+ vbflash_status = 1;
+
+ return sysfs_emit(buf, "0x%x\n", vbflash_status);
+}
+
static const struct bin_attribute psp_vbflash_bin_attr = {
.attr = {.name = "psp_vbflash", .mode = 0664},
.size = 0,
@@ -3531,6 +3550,8 @@ static const struct bin_attribute psp_vbflash_bin_attr = {
.read = amdgpu_psp_vbflash_read,
};
+static DEVICE_ATTR(psp_vbflash_status, 0444, amdgpu_psp_vbflash_status, NULL);
+
int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
{
int ret = 0;
@@ -3549,6 +3570,9 @@ int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
if (ret)
dev_err(adev->dev, "Failed to create device file psp_vbflash");
+ ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
+ if (ret)
+ dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
return ret;
default:
return 0;
@@ -3586,6 +3610,7 @@ static int psp_sysfs_init(struct amdgpu_device *adev)
void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
{
sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
+ device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
}
static void psp_sysfs_fini(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
index db7b7dbb9c93..e431f4994931 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h
@@ -130,6 +130,7 @@ struct psp_funcs
int (*load_usbc_pd_fw)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
int (*read_usbc_pd_fw)(struct psp_context *psp, uint32_t *fw_ver);
int (*update_spirom)(struct psp_context *psp, uint64_t fw_pri_mc_addr);
+ int (*vbflash_stat)(struct psp_context *psp);
};
#define AMDGPU_XGMI_MAX_CONNECTED_NODES 64
@@ -375,6 +376,7 @@ struct psp_context
char *vbflash_tmp_buf;
size_t vbflash_image_size;
+ bool vbflash_done;
};
struct amdgpu_psp_funcs {
@@ -425,6 +427,10 @@ struct amdgpu_psp_funcs {
((psp)->funcs->update_spirom ? \
(psp)->funcs->update_spirom((psp), fw_pri_mc_addr) : -EINVAL)
+#define psp_vbflash_status(psp) \
+ ((psp)->funcs->vbflash_stat ? \
+ (psp)->funcs->vbflash_stat((psp)) : -EINVAL)
+
extern const struct amd_ip_funcs psp_ip_funcs;
extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
index 894ac0c64bf6..c14abd9dd41e 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c
@@ -487,6 +487,9 @@ static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
/* Ring the doorbell */
WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
+ if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
+ return 0;
+
ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
MBOX_READY_FLAG, MBOX_READY_MASK, false);
if (ret) {
@@ -529,6 +532,8 @@ int psp_v13_0_update_spirom(struct psp_context *psp, uint64_t fw_pri_mc_addr)
if (ret)
return ret;
+ psp->vbflash_done = true;
+
ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
if (ret)
return ret;
@@ -536,6 +541,13 @@ int psp_v13_0_update_spirom(struct psp_context *psp, uint64_t fw_pri_mc_addr)
return 0;
}
+int psp_v13_0_vbflash_status(struct psp_context *psp)
+{
+ struct amdgpu_device *adev = psp->adev;
+
+ return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
+}
+
static const struct psp_funcs psp_v13_0_funcs = {
.init_microcode = psp_v13_0_init_microcode,
.bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
@@ -553,7 +565,8 @@ static const struct psp_funcs psp_v13_0_funcs = {
.ring_set_wptr = psp_v13_0_ring_set_wptr,
.load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
.read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
- .update_spirom = psp_v13_0_update_spirom
+ .update_spirom = psp_v13_0_update_spirom,
+ .vbflash_stat = psp_v13_0_vbflash_status
};
void psp_v13_0_set_psp_funcs(struct psp_context *psp)
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2022-05-05 20:06 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-05 20:05 [PATCH 1/4] drm/amd/psp: Add C2P registers to mp_13_0_2 header Alex Deucher
2022-05-05 20:05 ` [PATCH 2/4] drm/amdgpu/psp: Add VBIOS flash handler Alex Deucher
2022-05-05 20:05 ` [PATCH 3/4] drm/amdgpu/psp: Add vbflash sysfs interface support Alex Deucher
2022-05-05 20:05 ` [PATCH 4/4] drm/amdgpu: add sysfs to shows psp vbflash status Alex Deucher
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