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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 May 2022 19:07:10.8559 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 46627e03-98b7-41a9-f96e-08da31ef1ed2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT020.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6391 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher , Jack Xiao , Hawking Zhang Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" From: Jack Xiao a. use correct mes mqd settings b. fix me field in map_queue packet Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 7 +++++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 20 ++++++++++---------- 2 files changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 7614f38ff381..8a1bec70c719 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -145,16 +145,19 @@ static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, { uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); uint64_t wptr_addr = ring->wptr_gpu_addr; - uint32_t eng_sel = 0; + uint32_t me = 0, eng_sel = 0; switch (ring->funcs->type) { case AMDGPU_RING_TYPE_COMPUTE: + me = 1; eng_sel = 0; break; case AMDGPU_RING_TYPE_GFX: + me = 0; eng_sel = 4; break; case AMDGPU_RING_TYPE_MES: + me = 2; eng_sel = 5; break; default: @@ -168,7 +171,7 @@ static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring, PACKET3_MAP_QUEUES_VMID(0) | /* VMID */ PACKET3_MAP_QUEUES_QUEUE(ring->queue) | PACKET3_MAP_QUEUES_PIPE(ring->pipe) | - PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) | + PACKET3_MAP_QUEUES_ME((me)) | PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */ PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */ PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) | diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 5d4d54cabf70..fcf51947bb18 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -29,7 +29,7 @@ #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" #include "gc/gc_11_0_0_default.h" -#include "v10_structs.h" +#include "v11_structs.h" #include "mes_v11_api_def.h" MODULE_FIRMWARE("amdgpu/gc_11_0_0_mes.bin"); @@ -637,7 +637,7 @@ static int mes_v11_0_allocate_eop_buf(struct amdgpu_device *adev, static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) { - struct v10_compute_mqd *mqd = ring->mqd_ptr; + struct v11_compute_mqd *mqd = ring->mqd_ptr; uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; uint32_t tmp; @@ -724,22 +724,22 @@ static int mes_v11_0_mqd_init(struct amdgpu_ring *ring) mqd->cp_hqd_vmid = 0; /* activate the queue */ mqd->cp_hqd_active = 1; - mqd->cp_hqd_persistent_state = regCP_HQD_PERSISTENT_STATE_DEFAULT; + + tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; + tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, + PRELOAD_SIZE, 0x55); + mqd->cp_hqd_persistent_state = tmp; + mqd->cp_hqd_ib_control = regCP_HQD_IB_CONTROL_DEFAULT; mqd->cp_hqd_iq_timer = regCP_HQD_IQ_TIMER_DEFAULT; mqd->cp_hqd_quantum = regCP_HQD_QUANTUM_DEFAULT; - tmp = regCP_HQD_GFX_CONTROL_DEFAULT; - tmp = REG_SET_FIELD(tmp, CP_HQD_GFX_CONTROL, DB_UPDATED_MSG_EN, 1); - /* offset: 184 - this is used for CP_HQD_GFX_CONTROL */ - mqd->cp_hqd_suspend_cntl_stack_offset = tmp; - return 0; } static void mes_v11_0_queue_init_register(struct amdgpu_ring *ring) { - struct v10_compute_mqd *mqd = ring->mqd_ptr; + struct v11_compute_mqd *mqd = ring->mqd_ptr; struct amdgpu_device *adev = ring->adev; uint32_t data = 0; @@ -910,7 +910,7 @@ static int mes_v11_0_kiq_ring_init(struct amdgpu_device *adev) static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, enum admgpu_mes_pipe pipe) { - int r, mqd_size = sizeof(struct v10_compute_mqd); + int r, mqd_size = sizeof(struct v11_compute_mqd); struct amdgpu_ring *ring; if (pipe == AMDGPU_MES_KIQ_PIPE) -- 2.35.1