[PATCH 00/16] Remove entries from struct vba_vars_st

[PATCH 00/16] Remove entries from struct vba_vars_st

[Maíra Canal]

A while ago, I sent a patch removing some entries from the struct vba_vars_st
[1]. At that time, I used git grep and checked if they were used anywhere else
manually. But the struct vba_vars_st has more than 900 variables, so git grep
every variable is a pretty huge work. So, I grabbed all the variables' names
and put them in a text file, and wrote a bash script to analyze if the
variables were used.

I ended up finding a bunch of variables that were only assigned but never used.
I manually checked the results of the script in order to make sure that no
functional changes were made to the code.

I only removed variables that were only assigned but never used or variables
that were never even mentioned.

Best Regards,
- Maíra Canal

[1] https://lore.kernel.org/amd-gfx/20220630215316.1078841-1-mairacanal@riseup.net/T/#u

Maíra Canal (16):
  drm/amd/display: Remove NonUrgentLatencyTolerance VBA variable
  drm/amd/display: Remove CompBufReservedSpace* VBA variable
  drm/amd/display: Remove DSCCLK_calculated VBA variable
  drm/amd/display: Remove AllowDRAMSelfRefreshDuringVBlank VBA variable
  drm/amd/display: Remove VStartupMargin and FirstMainPlane VBA
    variables
  drm/amd/display: Remove ImmediateFlipSupportedSurface VBA variable
  drm/amd/display: Remove WritebackAllowFCLKChangeEndPosition VBA
    variable
  drm/amd/display: Remove some XFC variables from VBA
  drm/amd/display: Remove SwathWidthCSingleDPP VBA variable
  drm/amd/display: Remove ModeIsSupported VBA variable
  drm/amd/display: Remove MPCCombineEnable VBA variable
  drm/amd/display: Remove NumberOfDP2p0Support VBA variable
  drm/amd/display: Remove TFinalxFill VBA variable
  drm/amd/display: Remove MaximumDCCCompressionYSurface VBA variable
  drm/amd/display: Remove only mencioned once VBA variables
  drm/amd/display: Remove never used VBA variables

 .../dc/dml/dcn20/display_mode_vba_20.c        | 83 ++-----------------
 .../dc/dml/dcn20/display_mode_vba_20v2.c      | 83 ++-----------------
 .../dc/dml/dcn21/display_mode_vba_21.c        | 75 +----------------
 .../dc/dml/dcn30/display_mode_vba_30.c        | 43 ++--------
 .../dc/dml/dcn31/display_mode_vba_31.c        | 26 +-----
 .../dc/dml/dcn314/display_mode_vba_314.c      | 26 +-----
 .../dc/dml/dcn32/display_mode_vba_32.c        | 44 +---------
 .../drm/amd/display/dc/dml/display_mode_vba.c | 18 +---
 .../drm/amd/display/dc/dml/display_mode_vba.h | 45 ----------
 9 files changed, 30 insertions(+), 413 deletions(-)

-- 
2.37.1

[PATCH 01/16] drm/amd/display: Remove NonUrgentLatencyTolerance VBA variable

[Maíra Canal]

The NonUrgentLatencyTolerance variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the
NonUrgentLatencyTolerance entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c    | 4 ----
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c  | 4 ----
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c         | 1 -
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h         | 2 --
 4 files changed, 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d3b5b6fedf04..8a499f8066b7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -1768,10 +1768,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 				mode_lib->vba.UrgentLatencySupportUs[k]);
 	}
 
-	// Non-Urgent Latency Tolerance
-	mode_lib->vba.NonUrgentLatencyTolerance = mode_lib->vba.MinUrgentLatencySupportUs
-			- mode_lib->vba.UrgentWatermark;
-
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 63bbdf8b8678..ef7f0b8ed2d5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1804,10 +1804,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 				mode_lib->vba.UrgentLatencySupportUs[k]);
 	}
 
-	// Non-Urgent Latency Tolerance
-	mode_lib->vba.NonUrgentLatencyTolerance = mode_lib->vba.MinUrgentLatencySupportUs
-			- mode_lib->vba.UrgentWatermark;
-
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 503e7d984ff0..5dc2f52165fb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -102,7 +102,6 @@ dml_get_attr_func(stutter_efficiency_no_vblank, mode_lib->vba.StutterEfficiencyN
 dml_get_attr_func(stutter_period, mode_lib->vba.StutterPeriod);
 dml_get_attr_func(urgent_latency, mode_lib->vba.UrgentLatency);
 dml_get_attr_func(urgent_extra_latency, mode_lib->vba.UrgentExtraLatency);
-dml_get_attr_func(nonurgent_latency, mode_lib->vba.NonUrgentLatencyTolerance);
 dml_get_attr_func(dram_clock_change_latency, mode_lib->vba.MinActiveDRAMClockChangeLatencySupported);
 dml_get_attr_func(dispclk_calculated, mode_lib->vba.DISPCLK_calculated);
 dml_get_attr_func(total_data_read_bw, mode_lib->vba.TotalDataReadBandwidth);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 8460aefe7b6d..cb125f7d0814 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -50,7 +50,6 @@ dml_get_attr_decl(stutter_efficiency);
 dml_get_attr_decl(stutter_period);
 dml_get_attr_decl(urgent_latency);
 dml_get_attr_decl(urgent_extra_latency);
-dml_get_attr_decl(nonurgent_latency);
 dml_get_attr_decl(dram_clock_change_latency);
 dml_get_attr_decl(dispclk_calculated);
 dml_get_attr_decl(total_data_read_bw);
@@ -648,7 +647,6 @@ struct vba_vars_st {
 	double WritebackDRAMClockChangeWatermark;
 	double StutterEfficiency;
 	double StutterEfficiencyNotIncludingVBlank;
-	double NonUrgentLatencyTolerance;
 	double MinActiveDRAMClockChangeLatencySupported;
 	double Z8StutterEfficiencyBestCase;
 	unsigned int Z8NumberOfStutterBurstsPerFrameBestCase;
-- 
2.37.1

[PATCH 02/16] drm/amd/display: Remove CompBufReservedSpace* VBA variable

[Maíra Canal]

The variables CompBufReservedSpaceZs, CompBufReservedSpace64B and
CompBufReservedSpaceNeedAdjustment from the struct vba_vars_st are
only used on assignments, so their values are not used on code. Moreover,
their getter functions are not used also. So, remove the variables
entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c        | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h        | 5 -----
 3 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 573504de1789..a1fb2d1d1cdb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -307,9 +307,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 					 .dummy_boolean); /* bool *ViewportSizeSupport */
 	}
 
-	v->CompBufReservedSpaceZs     = v->CompBufReservedSpaceKBytes * 1024.0 / 256.0;
-	v->CompBufReservedSpace64B    = v->CompBufReservedSpaceKBytes * 1024.0 / 64.0;
-
 	// DCFCLK Deep Sleep
 	dml32_CalculateDCFCLKDeepSleep(
 			mode_lib->vba.NumberOfActiveSurfaces,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 5dc2f52165fb..d1c720b48b0c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -122,8 +122,6 @@ dml_get_attr_func(fclk_watermark, mode_lib->vba.Watermark.FCLKChangeWatermark);
 dml_get_attr_func(usr_retraining_watermark, mode_lib->vba.Watermark.USRRetrainingWatermark);
 
 dml_get_attr_func(comp_buffer_reserved_space_kbytes, mode_lib->vba.CompBufReservedSpaceKBytes);
-dml_get_attr_func(comp_buffer_reserved_space_64bytes, mode_lib->vba.CompBufReservedSpace64B);
-dml_get_attr_func(comp_buffer_reserved_space_zs, mode_lib->vba.CompBufReservedSpaceZs);
 dml_get_attr_func(unbounded_request_enabled, mode_lib->vba.UnboundedRequestEnabled);
 
 #define dml_get_pipe_attr_func(attr, var)  double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe) \
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index cb125f7d0814..632041cf49bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -67,8 +67,6 @@ dml_get_attr_decl(min_meta_chunk_size_in_byte);
 dml_get_attr_decl(fclk_watermark);
 dml_get_attr_decl(usr_retraining_watermark);
 dml_get_attr_decl(comp_buffer_reserved_space_kbytes);
-dml_get_attr_decl(comp_buffer_reserved_space_64bytes);
-dml_get_attr_decl(comp_buffer_reserved_space_zs);
 dml_get_attr_decl(unbounded_request_enabled);
 
 #define dml_get_pipe_attr_decl(attr) double get_##attr(struct display_mode_lib *mode_lib, const display_e2e_pipe_params_st *pipes, unsigned int num_pipes, unsigned int which_pipe)
@@ -655,9 +653,6 @@ struct vba_vars_st {
 	Watermarks      Watermark;
 	bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE;
 	unsigned int CompBufReservedSpaceKBytes;
-	unsigned int CompBufReservedSpace64B;
-	unsigned int CompBufReservedSpaceZs;
-	bool CompBufReservedSpaceNeedAdjustment;
 
 	// These are the clocks calcuated by the library but they are not actually
 	// used explicitly. They are fetched by tests and then possibly used. The
-- 
2.37.1

[PATCH 03/16] drm/amd/display: Remove DSCCLK_calculated VBA variable

[Maíra Canal]

The DSCCLK_calculated variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. Moreover,
its getter function is not used also. So, remove the DSCCLK_calculated
entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../dc/dml/dcn20/display_mode_vba_20.c        | 21 ++----------------
 .../dc/dml/dcn20/display_mode_vba_20v2.c      | 21 ++----------------
 .../dc/dml/dcn21/display_mode_vba_21.c        | 18 +--------------
 .../dc/dml/dcn30/display_mode_vba_30.c        | 19 ++--------------
 .../dc/dml/dcn31/display_mode_vba_31.c        | 19 ++--------------
 .../dc/dml/dcn314/display_mode_vba_314.c      | 19 ++--------------
 .../dc/dml/dcn32/display_mode_vba_32.c        | 22 ++-----------------
 .../drm/amd/display/dc/dml/display_mode_vba.c |  1 -
 .../drm/amd/display/dc/dml/display_mode_vba.h |  2 --
 9 files changed, 13 insertions(+), 129 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 8a499f8066b7..37a8b418a24d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -1770,28 +1770,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (mode_lib->vba.OutputFormat[k] == dm_420
-					|| mode_lib->vba.OutputFormat[k] == dm_n422)
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
+			if (mode_lib->vba.OutputFormat[k] == dm_420 || mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k])
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 6
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
-			else
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 3
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index ef7f0b8ed2d5..0e0697326717 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -1806,28 +1806,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			mode_lib->vba.DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (mode_lib->vba.OutputFormat[k] == dm_420
-					|| mode_lib->vba.OutputFormat[k] == dm_n422)
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
+			if (mode_lib->vba.OutputFormat[k] == dm_420 || mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k])
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 6
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
-			else
-				mode_lib->vba.DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 3
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 8a7485e21d53..aa752d78308f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -1764,28 +1764,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			locals->DSCCLK_calculated[k] = 0.0;
-		} else {
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
 			if (mode_lib->vba.OutputFormat[k] == dm_420
 					|| mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k])
-				locals->DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 6
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
-			else
-				locals->DSCCLK_calculated[k] =
-						mode_lib->vba.PixelClockBackEnd[k] / 3
-								/ mode_lib->vba.DSCFormatFactor
-								/ (1
-										- mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading
-												/ 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 876b321b30ca..cc9b6497b287 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -2159,26 +2159,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (v->OutputFormat[k] == dm_420)
-				v->DSCFormatFactor = 2;
-			else if (v->OutputFormat[k] == dm_444)
-				v->DSCFormatFactor = 1;
-			else if (v->OutputFormat[k] == dm_n422)
+		if ((v->BlendingAndTiming[k] == k) || v->DSCEnabled[k]) {
+			if (v->OutputFormat[k] == dm_420 || v->OutputFormat[k] == dm_n422)
 				v->DSCFormatFactor = 2;
 			else
 				v->DSCFormatFactor = 1;
-			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12
-					/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6
-					/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3
-					/ v->DSCFormatFactor / (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 3fab19134480..55ab4ec8b8fa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -2286,26 +2286,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (v->OutputFormat[k] == dm_420)
-				v->DSCFormatFactor = 2;
-			else if (v->OutputFormat[k] == dm_444)
-				v->DSCFormatFactor = 1;
-			else if (v->OutputFormat[k] == dm_n422)
+		if ((v->BlendingAndTiming[k] == k) || v->DSCEnabled[k]) {
+			if (v->OutputFormat[k] == dm_420 || v->OutputFormat[k] == dm_n422)
 				v->DSCFormatFactor = 2;
 			else
 				v->DSCFormatFactor = 1;
-			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index fc4d7474c111..279ed038a359 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -2310,26 +2310,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if ((v->BlendingAndTiming[k] != k) || !v->DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (v->OutputFormat[k] == dm_420)
-				v->DSCFormatFactor = 2;
-			else if (v->OutputFormat[k] == dm_444)
-				v->DSCFormatFactor = 1;
-			else if (v->OutputFormat[k] == dm_n422)
+		if ((v->BlendingAndTiming[k] == k) || v->DSCEnabled[k]) {
+			if (v->OutputFormat[k] == dm_420 || v->OutputFormat[k] == dm_n422)
 				v->DSCFormatFactor = 2;
 			else
 				v->DSCFormatFactor = 1;
-			if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (v->ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 / v->DSCFormatFactor
-						/ (1 - v->DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index a1fb2d1d1cdb..f199ef475ed0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -332,29 +332,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 
 	// DSCCLK
 	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
-		if ((mode_lib->vba.BlendingAndTiming[k] != k) || !mode_lib->vba.DSCEnabled[k]) {
-			v->DSCCLK_calculated[k] = 0.0;
-		} else {
-			if (mode_lib->vba.OutputFormat[k] == dm_420)
-				mode_lib->vba.DSCFormatFactor = 2;
-			else if (mode_lib->vba.OutputFormat[k] == dm_444)
-				mode_lib->vba.DSCFormatFactor = 1;
-			else if (mode_lib->vba.OutputFormat[k] == dm_n422)
+		if ((mode_lib->vba.BlendingAndTiming[k] == k) || mode_lib->vba.DSCEnabled[k]) {
+			if (mode_lib->vba.OutputFormat[k] == dm_420 || mode_lib->vba.OutputFormat[k] == dm_n422)
 				mode_lib->vba.DSCFormatFactor = 2;
 			else
 				mode_lib->vba.DSCFormatFactor = 1;
-			if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_4to1)
-				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 12
-						/ mode_lib->vba.DSCFormatFactor
-						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else if (mode_lib->vba.ODMCombineEnabled[k] == dm_odm_combine_mode_2to1)
-				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 6
-						/ mode_lib->vba.DSCFormatFactor
-						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
-			else
-				v->DSCCLK_calculated[k] = mode_lib->vba.PixelClockBackEnd[k] / 3
-						/ mode_lib->vba.DSCFormatFactor
-						/ (1 - mode_lib->vba.DISPCLKDPPCLKDSCCLKDownSpreading / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index d1c720b48b0c..316153ece160 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -134,7 +134,6 @@ dml_get_attr_func(unbounded_request_enabled, mode_lib->vba.UnboundedRequestEnabl
 
 dml_get_pipe_attr_func(dsc_delay, mode_lib->vba.DSCDelay);
 dml_get_pipe_attr_func(dppclk_calculated, mode_lib->vba.DPPCLK_calculated);
-dml_get_pipe_attr_func(dscclk_calculated, mode_lib->vba.DSCCLK_calculated);
 dml_get_pipe_attr_func(min_ttu_vblank, mode_lib->vba.MinTTUVBlank);
 dml_get_pipe_attr_func(min_ttu_vblank_in_us, mode_lib->vba.MinTTUVBlank);
 dml_get_pipe_attr_func(vratio_prefetch_l, mode_lib->vba.VRatioPrefetchY);
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 632041cf49bb..1b037e74bfc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -73,7 +73,6 @@ dml_get_attr_decl(unbounded_request_enabled);
 
 dml_get_pipe_attr_decl(dsc_delay);
 dml_get_pipe_attr_decl(dppclk_calculated);
-dml_get_pipe_attr_decl(dscclk_calculated);
 dml_get_pipe_attr_decl(min_ttu_vblank);
 dml_get_pipe_attr_decl(min_ttu_vblank_in_us);
 dml_get_pipe_attr_decl(vratio_prefetch_l);
@@ -1033,7 +1032,6 @@ struct vba_vars_st {
 	double PrefetchSourceLinesC[DC__NUM_DPP__MAX];
 	double PSCL_THROUGHPUT_LUMA[DC__NUM_DPP__MAX];
 	double PSCL_THROUGHPUT_CHROMA[DC__NUM_DPP__MAX];
-	double DSCCLK_calculated[DC__NUM_DPP__MAX];
 	unsigned int DSCDelay[DC__NUM_DPP__MAX];
 	unsigned int MaxVStartupLines[DC__NUM_DPP__MAX];
 	double DPPCLKUsingSingleDPP[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 04/16] drm/amd/display: Remove AllowDRAMSelfRefreshDuringVBlank VBA variable

[Maíra Canal]

The AllowDRAMSelfRefreshDuringVBlank variable from the struct vba_vars_st
is only used on assignments, so its value is not used on code. So, remove
it the AllowDRAMSelfRefreshDuringVBlank entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 3 ---
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h          | 1 -
 7 files changed, 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 37a8b418a24d..d86d5c346e42 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2350,7 +2350,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
 			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
-			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			mode_lib->vba.MinTTUVBlank[k] = dml_max(
 					mode_lib->vba.DRAMClockChangeWatermark,
 					dml_max(
@@ -2358,13 +2357,11 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 							mode_lib->vba.UrgentWatermark));
 		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
 			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
-			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			mode_lib->vba.MinTTUVBlank[k] = dml_max(
 					mode_lib->vba.StutterEnterPlusExitWatermark,
 					mode_lib->vba.UrgentWatermark);
 		} else {
 			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
-			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
 			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
 		}
 		if (!mode_lib->vba.DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 0e0697326717..effd02574a0e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2384,7 +2384,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
 			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = true;
-			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			mode_lib->vba.MinTTUVBlank[k] = dml_max(
 					mode_lib->vba.DRAMClockChangeWatermark,
 					dml_max(
@@ -2392,13 +2391,11 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 							mode_lib->vba.UrgentWatermark));
 		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
 			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
-			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			mode_lib->vba.MinTTUVBlank[k] = dml_max(
 					mode_lib->vba.StutterEnterPlusExitWatermark,
 					mode_lib->vba.UrgentWatermark);
 		} else {
 			mode_lib->vba.AllowDRAMClockChangeDuringVBlank[k] = false;
-			mode_lib->vba.AllowDRAMSelfRefreshDuringVBlank[k] = false;
 			mode_lib->vba.MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
 		}
 		if (!mode_lib->vba.DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index aa752d78308f..ae03f1a3c9f0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -2546,7 +2546,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
 		if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 0) {
 			locals->AllowDRAMClockChangeDuringVBlank[k] = true;
-			locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			locals->MinTTUVBlank[k] = dml_max(
 					mode_lib->vba.DRAMClockChangeWatermark,
 					dml_max(
@@ -2554,13 +2553,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 							mode_lib->vba.UrgentWatermark));
 		} else if (mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb] == 1) {
 			locals->AllowDRAMClockChangeDuringVBlank[k] = false;
-			locals->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			locals->MinTTUVBlank[k] = dml_max(
 					mode_lib->vba.StutterEnterPlusExitWatermark,
 					mode_lib->vba.UrgentWatermark);
 		} else {
 			locals->AllowDRAMClockChangeDuringVBlank[k] = false;
-			locals->AllowDRAMSelfRefreshDuringVBlank[k] = false;
 			locals->MinTTUVBlank[k] = mode_lib->vba.UrgentWatermark;
 		}
 		if (!mode_lib->vba.DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index cc9b6497b287..fe7fcb0d7b1f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -2972,7 +2972,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
 		if (PrefetchMode == 0) {
 			v->AllowDRAMClockChangeDuringVBlank[k] = true;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			v->MinTTUVBlank[k] = dml_max(
 					v->DRAMClockChangeWatermark,
 					dml_max(
@@ -2980,13 +2979,11 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 							v->UrgentWatermark));
 		} else if (PrefetchMode == 1) {
 			v->AllowDRAMClockChangeDuringVBlank[k] = false;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			v->MinTTUVBlank[k] = dml_max(
 					v->StutterEnterPlusExitWatermark,
 					v->UrgentWatermark);
 		} else {
 			v->AllowDRAMClockChangeDuringVBlank[k] = false;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
 			v->MinTTUVBlank[k] = v->UrgentWatermark;
 		}
 		if (!v->DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 55ab4ec8b8fa..eca05bbc0fb5 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -3185,17 +3185,14 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
 		if (PrefetchMode == 0) {
 			v->AllowDRAMClockChangeDuringVBlank[k] = true;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			v->MinTTUVBlank[k] = dml_max(
 					v->DRAMClockChangeWatermark,
 					dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
 		} else if (PrefetchMode == 1) {
 			v->AllowDRAMClockChangeDuringVBlank[k] = false;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
 		} else {
 			v->AllowDRAMClockChangeDuringVBlank[k] = false;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
 			v->MinTTUVBlank[k] = v->UrgentWatermark;
 		}
 		if (!v->DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 279ed038a359..acb47cdaaa05 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -3209,17 +3209,14 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
 		if (PrefetchMode == 0) {
 			v->AllowDRAMClockChangeDuringVBlank[k] = true;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			v->MinTTUVBlank[k] = dml_max(
 					v->DRAMClockChangeWatermark,
 					dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark));
 		} else if (PrefetchMode == 1) {
 			v->AllowDRAMClockChangeDuringVBlank[k] = false;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = true;
 			v->MinTTUVBlank[k] = dml_max(v->StutterEnterPlusExitWatermark, v->UrgentWatermark);
 		} else {
 			v->AllowDRAMClockChangeDuringVBlank[k] = false;
-			v->AllowDRAMSelfRefreshDuringVBlank[k] = false;
 			v->MinTTUVBlank[k] = v->UrgentWatermark;
 		}
 		if (!v->DynamicMetadataEnable[k])
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 1b037e74bfc3..f03cf9cf9096 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1004,7 +1004,6 @@ struct vba_vars_st {
 	double DSTYAfterScaler[DC__NUM_DPP__MAX];
 	double DSTXAfterScaler[DC__NUM_DPP__MAX];
 	bool AllowDRAMClockChangeDuringVBlank[DC__NUM_DPP__MAX];
-	bool AllowDRAMSelfRefreshDuringVBlank[DC__NUM_DPP__MAX];
 	double VRatioPrefetchY[DC__NUM_DPP__MAX];
 	double VRatioPrefetchC[DC__NUM_DPP__MAX];
 	double DestinationLinesForPrefetch[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 05/16] drm/amd/display: Remove VStartupMargin and FirstMainPlane VBA variables

[Maíra Canal]

The variables VStartupMargin and FirstMainPlane from the struct
vba_vars_st are only used on assignments, so there values are not used
on code. So, remove the variables entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../display/dc/dml/dcn20/display_mode_vba_20.c  | 14 +++-----------
 .../dc/dml/dcn20/display_mode_vba_20v2.c        | 14 +++-----------
 .../display/dc/dml/dcn30/display_mode_vba_30.c  | 17 ++++++-----------
 .../drm/amd/display/dc/dml/display_mode_vba.h   |  2 --
 4 files changed, 12 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index d86d5c346e42..1424aa7a5018 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2662,19 +2662,12 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 		}
 	}
 	{
-		unsigned int VStartupMargin = 0;
 		bool FirstMainPlane = true;
 
 		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-			if (mode_lib->vba.BlendingAndTiming[k] == k) {
-				unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
-						* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
-
-				if (FirstMainPlane) {
-					VStartupMargin = Margin;
-					FirstMainPlane = false;
-				} else
-					VStartupMargin = dml_min(VStartupMargin, Margin);
+			if (mode_lib->vba.BlendingAndTiming[k] == k && FirstMainPlane) {
+				FirstMainPlane = false;
+			}
 		}
 
 		if (mode_lib->vba.UseMaximumVStartup) {
@@ -2685,7 +2678,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 		}
 	}
 }
-}
 
 static void dml20_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index effd02574a0e..03613dbb3e61 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2735,19 +2735,12 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 		}
 	}
 	{
-		unsigned int VStartupMargin = 0;
 		bool FirstMainPlane = true;
 
 		for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-			if (mode_lib->vba.BlendingAndTiming[k] == k) {
-				unsigned int Margin = (mode_lib->vba.MaxVStartupLines[k] - mode_lib->vba.VStartup[k])
-						* mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k];
-
-				if (FirstMainPlane) {
-					VStartupMargin = Margin;
-					FirstMainPlane = false;
-				} else
-					VStartupMargin = dml_min(VStartupMargin, Margin);
+			if (mode_lib->vba.BlendingAndTiming[k] == k && FirstMainPlane) {
+				FirstMainPlane = false;
+			}
 		}
 
 		if (mode_lib->vba.UseMaximumVStartup) {
@@ -2758,7 +2751,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 		}
 	}
 }
-}
 
 static void dml20v2_DisplayPipeConfiguration(struct display_mode_lib *mode_lib)
 {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index fe7fcb0d7b1f..caa3a9c598ce 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3028,17 +3028,12 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	}
 
 	// VStartup Margin
-	v->VStartupMargin = 0;
-	v->FirstMainPlane = true;
-	for (k = 0; k < v->NumberOfActivePlanes; ++k) {
-		if (v->BlendingAndTiming[k] == k) {
-			double margin = (v->MaxVStartupLines[k] - v->VStartup[k]) * v->HTotal[k]
-					/ v->PixelClock[k];
-			if (v->FirstMainPlane == true) {
-				v->VStartupMargin = margin;
-				v->FirstMainPlane = false;
-			} else {
-				v->VStartupMargin = dml_min(v->VStartupMargin, margin);
+	{
+		bool FirstMainPlane = true;
+
+		for (k = 0; k < v->NumberOfActivePlanes; ++k) {
+			if (v->BlendingAndTiming[k] == k && FirstMainPlane) {
+				FirstMainPlane = false;
 			}
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index f03cf9cf9096..841a05bea57e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1106,7 +1106,6 @@ struct vba_vars_st {
 	double TimePerChromaMetaChunkFlip[DC__NUM_DPP__MAX];
 	unsigned int DCCCMaxUncompressedBlock[DC__NUM_DPP__MAX];
 	unsigned int DCCCMaxCompressedBlock[DC__NUM_DPP__MAX];
-	double VStartupMargin;
 	bool NotEnoughTimeForDynamicMetadata[DC__NUM_DPP__MAX];
 
 	/* Missing from VBA */
@@ -1137,7 +1136,6 @@ struct vba_vars_st {
 	double MinUrgentLatencySupportUs;
 	double MinFullDETBufferingTime;
 	double AverageReadBandwidthGBytePerSecond;
-	bool   FirstMainPlane;
 
 	unsigned int ViewportWidthChroma[DC__NUM_DPP__MAX];
 	unsigned int ViewportHeightChroma[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 06/16] drm/amd/display: Remove ImmediateFlipSupportedSurface VBA variable

[Maíra Canal]

The ImmediateFlipSupportedSurface variable from the struct
vba_vars_st is only used on assignments, so its value is not used
on code. So, remove the ImmediateFlipSupportedSurface entry from the struct
vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 6 ------
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h       | 2 --
 2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index f199ef475ed0..e2e1d6e77902 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -355,12 +355,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			if (j != k && mode_lib->vba.BlendingAndTiming[k] == j && mode_lib->vba.DSCEnabled[j])
 				v->DSCDelay[k] = v->DSCDelay[j];
 
-	//Immediate Flip
-	for (k = 0; k < mode_lib->vba.NumberOfActiveSurfaces; ++k) {
-		v->ImmediateFlipSupportedSurface[k] = mode_lib->vba.ImmediateFlipSupport
-				&& (mode_lib->vba.ImmediateFlipRequirement[k] != dm_immediate_flip_not_required);
-	}
-
 	// Prefetch
 	dml32_CalculateSurfaceSizeInMall(
 				mode_lib->vba.NumberOfActiveSurfaces,
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 841a05bea57e..76cba5d7ac10 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -659,8 +659,6 @@ struct vba_vars_st {
 	double DISPCLK_calculated;
 	double DPPCLK_calculated[DC__NUM_DPP__MAX];
 
-	bool ImmediateFlipSupportedSurface[DC__NUM_DPP__MAX];
-
 	bool Use_One_Row_For_Frame[DC__NUM_DPP__MAX];
 	bool Use_One_Row_For_Frame_Flip[DC__NUM_DPP__MAX];
 	unsigned int VUpdateOffsetPix[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 07/16] drm/amd/display: Remove WritebackAllowFCLKChangeEndPosition VBA variable

[Maíra Canal]

The WritebackAllowFCLKChangeEndPosition variable from the struct
vba_vars_st is only used on assignments, so its value is not used on
code. So, remove the WritebackAllowFCLKChangeEndPosition entry
from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c    | 4 ----
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h         | 1 -
 2 files changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index e2e1d6e77902..756a55f69799 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1219,12 +1219,8 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 				v->WritebackAllowDRAMClockChangeEndPosition[k] = dml_max(0,
 						v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
 								- v->Watermark.WritebackDRAMClockChangeWatermark);
-				v->WritebackAllowFCLKChangeEndPosition[k] = dml_max(0,
-						v->VStartup[k] * mode_lib->vba.HTotal[k] / mode_lib->vba.PixelClock[k]
-								- v->Watermark.WritebackFCLKChangeWatermark);
 			} else {
 				v->WritebackAllowDRAMClockChangeEndPosition[k] = 0;
-				v->WritebackAllowFCLKChangeEndPosition[k] = 0;
 			}
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 76cba5d7ac10..518e599d74e2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1303,7 +1303,6 @@ struct vba_vars_st {
 	bool OutputMultistreamEn[DC__NUM_DPP__MAX];
 	bool UsesMALLForStaticScreen[DC__NUM_DPP__MAX];
 	double MaxActiveDRAMClockChangeLatencySupported[DC__NUM_DPP__MAX];
-	double WritebackAllowFCLKChangeEndPosition[DC__NUM_DPP__MAX];
 	bool PTEBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
 	bool DCCMetaBufferSizeNotExceededPerState[DC__NUM_DPP__MAX]; // new in DML32
 	bool NotEnoughDSCSlices[DC__VOLTAGE_STATES];
-- 
2.37.1

[PATCH 08/16] drm/amd/display: Remove some XFC variables from VBA

[Maíra Canal]

The variables XFCSupported, XFCTSlvVupdateOffset, XFCSlaveVupdateWidth,
XFCSlaveVReadyOffset, XFCTransferDelay, XFCPrechargeDelay,
XFCRemoteSurfaceFlipLatency and XFCPrefetchMargin are are only
used on assignments, so their values are not used on code. So, remove
the variables entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../dc/dml/dcn20/display_mode_vba_20.c        | 38 -------------------
 .../dc/dml/dcn20/display_mode_vba_20v2.c      | 38 -------------------
 .../dc/dml/dcn21/display_mode_vba_21.c        | 38 -------------------
 .../drm/amd/display/dc/dml/display_mode_vba.c |  1 -
 .../drm/amd/display/dc/dml/display_mode_vba.h |  8 ----
 5 files changed, 123 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 1424aa7a5018..7effe4be61b2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2580,9 +2580,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 		if (mode_lib->vba.XFCEnabled[k] == true) {
 			double TWait;
 
-			mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
-			mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
-			mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
 			TWait = CalculateTWait(
 					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
 					mode_lib->vba.DRAMClockChangeLatency,
@@ -2606,26 +2603,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 					&mode_lib->vba.SrcActiveDrainRate,
 					&mode_lib->vba.TInitXFill,
 					&mode_lib->vba.TslvChk);
-			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
-					dml_floor(
-							mode_lib->vba.XFCRemoteSurfaceFlipDelay
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
-			mode_lib->vba.XFCTransferDelay[k] =
-					dml_ceil(
-							mode_lib->vba.XFCBusTransportTime
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
-			mode_lib->vba.XFCPrechargeDelay[k] =
-					dml_ceil(
-							(mode_lib->vba.XFCBusTransportTime
-									+ mode_lib->vba.TInitXFill
-									+ mode_lib->vba.TslvChk)
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
 			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
 					* mode_lib->vba.SrcActiveDrainRate;
 			mode_lib->vba.FinalFillMargin =
@@ -2644,21 +2621,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
 					/ (mode_lib->vba.SrcActiveDrainRate
 							* mode_lib->vba.XFCFillBWOverhead / 100);
-			mode_lib->vba.XFCPrefetchMargin[k] =
-					mode_lib->vba.XFCRemoteSurfaceFlipDelay
-							+ mode_lib->vba.TFinalxFill
-							+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
-									+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
-									* mode_lib->vba.HTotal[k]
-									/ mode_lib->vba.PixelClock[k];
-		} else {
-			mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
-			mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
-			mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
-			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
-			mode_lib->vba.XFCPrechargeDelay[k] = 0;
-			mode_lib->vba.XFCTransferDelay[k] = 0;
-			mode_lib->vba.XFCPrefetchMargin[k] = 0;
 		}
 	}
 	{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index 03613dbb3e61..a23b400f615b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2653,9 +2653,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 		if (mode_lib->vba.XFCEnabled[k] == true) {
 			double TWait;
 
-			mode_lib->vba.XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
-			mode_lib->vba.XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
-			mode_lib->vba.XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
 			TWait = CalculateTWait(
 					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
 					mode_lib->vba.DRAMClockChangeLatency,
@@ -2679,26 +2676,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 					&mode_lib->vba.SrcActiveDrainRate,
 					&mode_lib->vba.TInitXFill,
 					&mode_lib->vba.TslvChk);
-			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] =
-					dml_floor(
-							mode_lib->vba.XFCRemoteSurfaceFlipDelay
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
-			mode_lib->vba.XFCTransferDelay[k] =
-					dml_ceil(
-							mode_lib->vba.XFCBusTransportTime
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
-			mode_lib->vba.XFCPrechargeDelay[k] =
-					dml_ceil(
-							(mode_lib->vba.XFCBusTransportTime
-									+ mode_lib->vba.TInitXFill
-									+ mode_lib->vba.TslvChk)
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
 			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
 					* mode_lib->vba.SrcActiveDrainRate;
 			mode_lib->vba.FinalFillMargin =
@@ -2717,21 +2694,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
 					/ (mode_lib->vba.SrcActiveDrainRate
 							* mode_lib->vba.XFCFillBWOverhead / 100);
-			mode_lib->vba.XFCPrefetchMargin[k] =
-					mode_lib->vba.XFCRemoteSurfaceFlipDelay
-							+ mode_lib->vba.TFinalxFill
-							+ (mode_lib->vba.DestinationLinesToRequestVMInVBlank[k]
-									+ mode_lib->vba.DestinationLinesToRequestRowInVBlank[k])
-									* mode_lib->vba.HTotal[k]
-									/ mode_lib->vba.PixelClock[k];
-		} else {
-			mode_lib->vba.XFCSlaveVUpdateOffset[k] = 0;
-			mode_lib->vba.XFCSlaveVupdateWidth[k] = 0;
-			mode_lib->vba.XFCSlaveVReadyOffset[k] = 0;
-			mode_lib->vba.XFCRemoteSurfaceFlipLatency[k] = 0;
-			mode_lib->vba.XFCPrechargeDelay[k] = 0;
-			mode_lib->vba.XFCTransferDelay[k] = 0;
-			mode_lib->vba.XFCPrefetchMargin[k] = 0;
 		}
 	}
 	{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index ae03f1a3c9f0..4ba9fa17ea39 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -2589,9 +2589,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 		if (mode_lib->vba.XFCEnabled[k] == true) {
 			double TWait;
 
-			locals->XFCSlaveVUpdateOffset[k] = mode_lib->vba.XFCTSlvVupdateOffset;
-			locals->XFCSlaveVupdateWidth[k] = mode_lib->vba.XFCTSlvVupdateWidth;
-			locals->XFCSlaveVReadyOffset[k] = mode_lib->vba.XFCTSlvVreadyOffset;
 			TWait = CalculateTWait(
 					mode_lib->vba.PrefetchMode[mode_lib->vba.VoltageLevel][mode_lib->vba.maxMpcComb],
 					mode_lib->vba.DRAMClockChangeLatency,
@@ -2615,26 +2612,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 					&mode_lib->vba.SrcActiveDrainRate,
 					&mode_lib->vba.TInitXFill,
 					&mode_lib->vba.TslvChk);
-					locals->XFCRemoteSurfaceFlipLatency[k] =
-					dml_floor(
-							mode_lib->vba.XFCRemoteSurfaceFlipDelay
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
-			locals->XFCTransferDelay[k] =
-					dml_ceil(
-							mode_lib->vba.XFCBusTransportTime
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
-			locals->XFCPrechargeDelay[k] =
-					dml_ceil(
-							(mode_lib->vba.XFCBusTransportTime
-									+ mode_lib->vba.TInitXFill
-									+ mode_lib->vba.TslvChk)
-									/ (mode_lib->vba.HTotal[k]
-											/ mode_lib->vba.PixelClock[k]),
-							1);
 			mode_lib->vba.InitFillLevel = mode_lib->vba.XFCXBUFLatencyTolerance
 					* mode_lib->vba.SrcActiveDrainRate;
 			mode_lib->vba.FinalFillMargin =
@@ -2653,21 +2630,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
 					/ (mode_lib->vba.SrcActiveDrainRate
 							* mode_lib->vba.XFCFillBWOverhead / 100);
-			locals->XFCPrefetchMargin[k] =
-					mode_lib->vba.XFCRemoteSurfaceFlipDelay
-							+ mode_lib->vba.TFinalxFill
-							+ (locals->DestinationLinesToRequestVMInVBlank[k]
-									+ locals->DestinationLinesToRequestRowInVBlank[k])
-									* mode_lib->vba.HTotal[k]
-									/ mode_lib->vba.PixelClock[k];
-		} else {
-			locals->XFCSlaveVUpdateOffset[k] = 0;
-			locals->XFCSlaveVupdateWidth[k] = 0;
-			locals->XFCSlaveVReadyOffset[k] = 0;
-			locals->XFCRemoteSurfaceFlipLatency[k] = 0;
-			locals->XFCPrechargeDelay[k] = 0;
-			locals->XFCTransferDelay[k] = 0;
-			locals->XFCPrefetchMargin[k] = 0;
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 316153ece160..7a4a013f195a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -489,7 +489,6 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.ODMCapability = ip->odm_capable;
 	mode_lib->vba.DISPCLKRampingMargin = ip->dispclk_ramp_margin_percent;
 
-	mode_lib->vba.XFCSupported = ip->xfc_supported;
 	mode_lib->vba.XFCFillBWOverhead = ip->xfc_fill_bw_overhead_percent;
 	mode_lib->vba.XFCFillConstant = ip->xfc_fill_constant_bytes;
 	mode_lib->vba.DPPCLKDelaySubtotal = ip->dppclk_delay_subtotal;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 518e599d74e2..91562c0d35f2 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -497,7 +497,6 @@ struct vba_vars_st {
 	unsigned int PTEBufferSizeInRequestsChroma;
 	double DISPCLKRampingMargin;
 	unsigned int MaxInterDCNTileRepeaters;
-	bool XFCSupported;
 	double XFCSlvChunkSize;
 	double XFCFillBWOverhead;
 	double XFCFillConstant;
@@ -1041,13 +1040,6 @@ struct vba_vars_st {
 	unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
 	unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
 	unsigned int BlockWidth256BytesC[DC__NUM_DPP__MAX];
-	double XFCSlaveVUpdateOffset[DC__NUM_DPP__MAX];
-	double XFCSlaveVupdateWidth[DC__NUM_DPP__MAX];
-	double XFCSlaveVReadyOffset[DC__NUM_DPP__MAX];
-	double XFCTransferDelay[DC__NUM_DPP__MAX];
-	double XFCPrechargeDelay[DC__NUM_DPP__MAX];
-	double XFCRemoteSurfaceFlipLatency[DC__NUM_DPP__MAX];
-	double XFCPrefetchMargin[DC__NUM_DPP__MAX];
 	unsigned int dpte_row_width_luma_ub[DC__NUM_DPP__MAX];
 	unsigned int dpte_row_width_chroma_ub[DC__NUM_DPP__MAX];
 	double FullDETBufferingTimeY[DC__NUM_DPP__MAX];                     // WM
-- 
2.37.1

[PATCH 09/16] drm/amd/display: Remove SwathWidthCSingleDPP VBA variable

[Maíra Canal]

The SwathWidthCSingleDPP variable from the struct vba_vars_st is only
used on assignments, so its value is not used on code. So, remove the
SwathWidthCSingleDPP entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 2 --
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c    | 2 --
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h           | 1 -
 5 files changed, 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index caa3a9c598ce..4fac83c776ad 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -3660,10 +3660,8 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
 		if (v->SourceScan[k] != dm_vert) {
 			v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
-			v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
 		} else {
 			v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
-			v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
 		}
 	}
 	for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index eca05bbc0fb5..9ea2d2fd56f1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -3965,10 +3965,8 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	for (k = 0; k < v->NumberOfActivePlanes; k++) {
 		if (v->SourceScan[k] != dm_vert) {
 			v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
-			v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
 		} else {
 			v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
-			v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
 		}
 	}
 	for (k = 0; k < v->NumberOfActivePlanes; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index acb47cdaaa05..ae749d39db2a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -4077,10 +4077,8 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
 	for (k = 0; k < v->NumberOfActivePlanes; k++) {
 		if (v->SourceScan[k] != dm_vert) {
 			v->SwathWidthYSingleDPP[k] = v->ViewportWidth[k];
-			v->SwathWidthCSingleDPP[k] = v->ViewportWidthChroma[k];
 		} else {
 			v->SwathWidthYSingleDPP[k] = v->ViewportHeight[k];
-			v->SwathWidthCSingleDPP[k] = v->ViewportHeightChroma[k];
 		}
 	}
 	for (k = 0; k < v->NumberOfActivePlanes; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 756a55f69799..a88cfce3b771 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -1721,10 +1721,8 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
 		if (!IsVertical(mode_lib->vba.SourceRotation[k])) {
 			v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportWidth[k];
-			v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportWidthChroma[k];
 		} else {
 			v->SwathWidthYSingleDPP[k] = mode_lib->vba.ViewportHeight[k];
-			v->SwathWidthCSingleDPP[k] = mode_lib->vba.ViewportHeightChroma[k];
 		}
 	}
 	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 91562c0d35f2..ac8131b52b78 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -939,7 +939,6 @@ struct vba_vars_st {
 
 
 	bool           MPCCombine[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-	double         SwathWidthCSingleDPP[DC__NUM_DPP__MAX];
 	double         MaximumSwathWidthInLineBufferLuma;
 	double         MaximumSwathWidthInLineBufferChroma;
 	double         MaximumSwathWidthLuma[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 10/16] drm/amd/display: Remove ModeIsSupported VBA variable

[Maíra Canal]

The ModeIsSupported variable from the struct vba_vars_st is only used on
assignments, so its value is not used on code. So, remove the
ModeIsSupported entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 1 -
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c    | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h           | 1 -
 5 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index 4fac83c776ad..b776a7940fac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5250,7 +5250,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		for (i = v->soc.num_states; i >= 0; i--) {
 			if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
 				v->VoltageLevel = i;
-				v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
 				if (v->ModeSupport[i][1] == true) {
 					MaximumMPCCombine = 1;
 				} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index 9ea2d2fd56f1..b338e72d96d8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5521,7 +5521,6 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		for (i = v->soc.num_states; i >= 0; i--) {
 			if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
 				v->VoltageLevel = i;
-				v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
 				if (v->ModeSupport[i][0] == true) {
 					MaximumMPCCombine = 0;
 				} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index ae749d39db2a..6c60731687bf 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5636,7 +5636,6 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
 		for (i = v->soc.num_states; i >= 0; i--) {
 			if (i == v->soc.num_states || v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true) {
 				v->VoltageLevel = i;
-				v->ModeIsSupported = v->ModeSupport[i][0] == true || v->ModeSupport[i][1] == true;
 				if (v->ModeSupport[i][0] == true) {
 					MaximumMPCCombine = 0;
 				} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index a88cfce3b771..5fce4bbb4e85 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3668,8 +3668,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		if (i == v->soc.num_states || mode_lib->vba.ModeSupport[i][0] == true ||
 				mode_lib->vba.ModeSupport[i][1] == true) {
 			mode_lib->vba.VoltageLevel = i;
-			mode_lib->vba.ModeIsSupported = mode_lib->vba.ModeSupport[i][0] == true
-					|| mode_lib->vba.ModeSupport[i][1] == true;
 
 			if (mode_lib->vba.ModeSupport[i][0] == true) {
 				MaximumMPCCombine = 0;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index ac8131b52b78..f4d4bf7b6111 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1132,7 +1132,6 @@ struct vba_vars_st {
 	double VRatioChroma[DC__NUM_DPP__MAX];
 	int WritebackSourceWidth[DC__NUM_DPP__MAX];
 
-	bool ModeIsSupported;
 	bool ODMCombine4To1Supported;
 
 	unsigned int SurfaceWidthY[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 11/16] drm/amd/display: Remove MPCCombineEnable VBA variable

[Maíra Canal]

The MPCCombineEnable variable from the struct vba_vars_st is only
used on assignments, so its value is not used on code. So, remove
the MPCCombineEnable entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c  | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c  | 1 -
 .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c    | 1 -
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c  | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h           | 1 -
 5 files changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
index b776a7940fac..7dd51fe88d4f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c
@@ -5259,7 +5259,6 @@ void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		}
 		v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
 		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-			v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
 			v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
 		}
 		v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
index b338e72d96d8..2e906f01950b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c
@@ -5530,7 +5530,6 @@ void dml31_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		}
 		v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
 		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-			v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
 			v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
 		}
 		v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
index 6c60731687bf..6a5b3c39ec60 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c
@@ -5645,7 +5645,6 @@ void dml314_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_
 		}
 		v->ImmediateFlipSupport = v->ImmediateFlipSupportedForState[v->VoltageLevel][MaximumMPCCombine];
 		for (k = 0; k <= v->NumberOfActivePlanes - 1; k++) {
-			v->MPCCombineEnable[k] = v->MPCCombine[v->VoltageLevel][MaximumMPCCombine][k];
 			v->DPPPerPlane[k] = v->NoOfDPP[v->VoltageLevel][MaximumMPCCombine][k];
 		}
 		v->DCFCLK = v->DCFCLKState[v->VoltageLevel][MaximumMPCCombine];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 5fce4bbb4e85..6d4907656f9f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3685,8 +3685,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 			mode_lib->vba.CompressedBufferSizeInkByteAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; // Not used, informational
 
 	for (k = 0; k <= mode_lib->vba.NumberOfActiveSurfaces - 1; k++) {
-		mode_lib->vba.MPCCombineEnable[k] =
-				mode_lib->vba.MPCCombine[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
 		mode_lib->vba.DPPPerPlane[k] = mode_lib->vba.NoOfDPP[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
 		mode_lib->vba.SwathHeightY[k] =
 				mode_lib->vba.SwathHeightYAllStates[mode_lib->vba.VoltageLevel][MaximumMPCCombine][k];
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index f4d4bf7b6111..31cf144860b9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1147,7 +1147,6 @@ struct vba_vars_st {
 	double GPUVMMinPageSize;
 	double HostVMMinPageSize;
 
-	bool   MPCCombineEnable[DC__NUM_DPP__MAX];
 	unsigned int HostVMMaxNonCachedPageTableLevels;
 	bool   DynamicMetadataVMEnabled;
 	double       WritebackInterfaceBufferSize;
-- 
2.37.1

[PATCH 12/16] drm/amd/display: Remove NumberOfDP2p0Support VBA variable

[Maíra Canal]

The NumberOfDP2p0Support variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. So,
remove the NumberOfDP2p0Support entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c | 2 --
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h          | 1 -
 2 files changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 6d4907656f9f..3c044549c95f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -2186,8 +2186,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 
 	mode_lib->vba.NumberOfOTGSupport = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveOTG <= mode_lib->vba.MaxNumOTG);
 	mode_lib->vba.NumberOfHDMIFRLSupport = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveHDMIFRL <= mode_lib->vba.MaxNumHDMIFRLOutputs);
-	mode_lib->vba.NumberOfDP2p0Support = (v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0 <= mode_lib->vba.MaxNumDP2p0Streams
-			&& v->dummy_vars.dml32_ModeSupportAndSystemConfigurationFull.TotalNumberOfActiveDP2p0Outputs <= mode_lib->vba.MaxNumDP2p0Outputs);
 
 	/* Display IO and DSC Support Check */
 	mode_lib->vba.NonsupportedDSCInputBPC = false;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 31cf144860b9..f973d0ee82f9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -754,7 +754,6 @@ struct vba_vars_st {
 	bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 	bool EnoughWritebackUnits;
 	bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
-	bool NumberOfDP2p0Support;
 	unsigned int MaxNumDP2p0Streams;
 	unsigned int MaxNumDP2p0Outputs;
 	enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 13/16] drm/amd/display: Remove TFinalxFill VBA variable

[Maíra Canal]

The TFinalxFill variable from the struct vba_vars_st is only used
on assignments, so its value is not used on code. So,
remove the TFinalxFill entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 ---
 .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c   | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 ---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h          | 1 -
 4 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
index 7effe4be61b2..91e74c0f3c3c 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c
@@ -2618,9 +2618,6 @@ static void dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPer
 			mode_lib->vba.RemainingFillLevel = dml_max(
 					0.0,
 					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
-			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
-					/ (mode_lib->vba.SrcActiveDrainRate
-							* mode_lib->vba.XFCFillBWOverhead / 100);
 		}
 	}
 	{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
index a23b400f615b..9b52f9f3e4a0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c
@@ -2691,9 +2691,6 @@ static void dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndP
 			mode_lib->vba.RemainingFillLevel = dml_max(
 					0.0,
 					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
-			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
-					/ (mode_lib->vba.SrcActiveDrainRate
-							* mode_lib->vba.XFCFillBWOverhead / 100);
 		}
 	}
 	{
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index 4ba9fa17ea39..bc8cc21cf3f6 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -2627,9 +2627,6 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 			mode_lib->vba.RemainingFillLevel = dml_max(
 					0.0,
 					mode_lib->vba.FinalFillLevel - mode_lib->vba.InitFillLevel);
-			mode_lib->vba.TFinalxFill = mode_lib->vba.RemainingFillLevel
-					/ (mode_lib->vba.SrcActiveDrainRate
-							* mode_lib->vba.XFCFillBWOverhead / 100);
 		}
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index f973d0ee82f9..46e69f941bff 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -421,7 +421,6 @@ struct vba_vars_st {
 	double FinalFillMargin;
 	double FinalFillLevel;
 	double RemainingFillLevel;
-	double TFinalxFill;
 
 	//
 	// SOC Bounding Box Parameters
-- 
2.37.1

[PATCH 14/16] drm/amd/display: Remove MaximumDCCCompressionYSurface VBA variable

[Maíra Canal]

The MaximumDCCCompressionYSurface variable from the struct vba_vars_st is
only used on assignments, so its value is not used on code. So,
remove the MaximumDCCCompressionYSurface entry from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../amd/display/dc/dml/dcn21/display_mode_vba_21.c  | 13 +++----------
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.h   |  1 -
 2 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
index bc8cc21cf3f6..7007b6e16e7d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c
@@ -143,7 +143,7 @@ static bool CalculatePrefetchSchedule(
 		double *VReadyOffsetPix);
 static double RoundToDFSGranularityUp(double Clock, double VCOSpeed);
 static double RoundToDFSGranularityDown(double Clock, double VCOSpeed);
-static double CalculateDCCConfiguration(
+static void CalculateDCCConfiguration(
 		bool                 DCCEnabled,
 		bool                 DCCProgrammingAssumesScanDirectionUnknown,
 		unsigned int         ViewportWidth,
@@ -1072,7 +1072,7 @@ static double RoundToDFSGranularityDown(double Clock, double VCOSpeed)
 	return VCOSpeed * 4 / dml_ceil(VCOSpeed * 4 / Clock, 1);
 }
 
-static double CalculateDCCConfiguration(
+static void CalculateDCCConfiguration(
 		bool DCCEnabled,
 		bool DCCProgrammingAssumesScanDirectionUnknown,
 		unsigned int ViewportWidth,
@@ -1087,7 +1087,6 @@ static double CalculateDCCConfiguration(
 		unsigned int *MaxCompressedBlock,
 		unsigned int *Independent64ByteBlock)
 {
-	double MaximumDCCCompressionSurface = 0.0;
 	enum {
 		REQ_256Bytes,
 		REQ_128BytesNonContiguous,
@@ -1185,25 +1184,19 @@ static double CalculateDCCConfiguration(
 		*MaxUncompressedBlock = 256;
 		*MaxCompressedBlock = 256;
 		*Independent64ByteBlock = false;
-		MaximumDCCCompressionSurface = 4.0;
 	} else if (Request == REQ_128BytesContiguous) {
 		*MaxUncompressedBlock = 128;
 		*MaxCompressedBlock = 128;
 		*Independent64ByteBlock = false;
-		MaximumDCCCompressionSurface = 2.0;
 	} else if (Request == REQ_128BytesNonContiguous) {
 		*MaxUncompressedBlock = 256;
 		*MaxCompressedBlock = 64;
 		*Independent64ByteBlock = true;
-		MaximumDCCCompressionSurface = 4.0;
 	} else {
 		*MaxUncompressedBlock = 0;
 		*MaxCompressedBlock = 0;
 		*Independent64ByteBlock = 0;
-		MaximumDCCCompressionSurface = 0.0;
 	}
-
-	return MaximumDCCCompressionSurface;
 }
 
 static double CalculatePrefetchSourceLines(
@@ -2568,7 +2561,7 @@ static void DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerforman
 	// DCC Configuration
 	mode_lib->vba.ActiveDPPs = 0;
 	for (k = 0; k < mode_lib->vba.NumberOfActivePlanes; ++k) {
-		locals->MaximumDCCCompressionYSurface[k] = CalculateDCCConfiguration(
+		CalculateDCCConfiguration(
 			mode_lib->vba.DCCEnable[k],
 			false, // We should always know the direction DCCProgrammingAssumesScanDirectionUnknown,
 			mode_lib->vba.ViewportWidth[k],
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 46e69f941bff..a07e97035dd1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -1032,7 +1032,6 @@ struct vba_vars_st {
 	unsigned int DCCYMaxUncompressedBlock[DC__NUM_DPP__MAX];
 	unsigned int DCCYMaxCompressedBlock[DC__NUM_DPP__MAX];
 	unsigned int DCCYIndependent64ByteBlock[DC__NUM_DPP__MAX];
-	double MaximumDCCCompressionYSurface[DC__NUM_DPP__MAX];
 	unsigned int BlockHeight256BytesY[DC__NUM_DPP__MAX];
 	unsigned int BlockHeight256BytesC[DC__NUM_DPP__MAX];
 	unsigned int BlockWidth256BytesY[DC__NUM_DPP__MAX];
-- 
2.37.1

[PATCH 15/16] drm/amd/display: Remove only mencioned once VBA variables

[Maíra Canal]

The variables PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE,
RefreshRate, FECEnable, ScalerRecoutWidth, MaxNumDP2p0Streams, and
MaxNumDP2p0Outputs are only used on assignments, so there values are not
used on code. So, remove the variables entries from the struct
vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 .../amd/display/dc/dml/dcn32/display_mode_vba_32.c  |  1 -
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.c   | 13 ++-----------
 .../gpu/drm/amd/display/dc/dml/display_mode_vba.h   |  6 ------
 3 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
index 3c044549c95f..e9c6cc45bfc3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_32.c
@@ -3715,7 +3715,6 @@ void dml32_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_l
 		}
 
 		mode_lib->vba.DSCEnabled[k] = mode_lib->vba.RequiresDSC[mode_lib->vba.VoltageLevel][k];
-		mode_lib->vba.FECEnable[k] = mode_lib->vba.RequiresFEC[mode_lib->vba.VoltageLevel][k];
 		mode_lib->vba.OutputBpp[k] = mode_lib->vba.OutputBppPerState[mode_lib->vba.VoltageLevel][k];
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
index 7a4a013f195a..1176a73813aa 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.c
@@ -340,7 +340,6 @@ static void fetch_socbb_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.SMNLatency = soc->smn_latency_us;
 	mode_lib->vba.MALLAllocatedForDCNFinal = soc->mall_allocated_for_dcn_mbytes;
 
-	mode_lib->vba.PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE = soc->pct_ideal_dram_bw_after_urgent_strobe;
 	mode_lib->vba.MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation =
 			soc->max_avg_fabric_bw_use_normal_percent;
 	mode_lib->vba.MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE =
@@ -441,11 +440,9 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
 	mode_lib->vba.CompbufReservedSpaceZs = ip->compbuf_reserved_space_zs;
 	mode_lib->vba.CompressedBufferSegmentSizeInkByteFinal = ip->compressed_buffer_segment_size_in_kbytes;
 	mode_lib->vba.LineBufferSizeFinal = ip->line_buffer_size_bits;
-	mode_lib->vba.AlphaPixelChunkSizeInKByte = ip->alpha_pixel_chunk_size_kbytes; // not ysed
-	mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes; // not used
+	mode_lib->vba.AlphaPixelChunkSizeInKByte = ip->alpha_pixel_chunk_size_kbytes;
+	mode_lib->vba.MinPixelChunkSizeBytes = ip->min_pixel_chunk_size_bytes;
 	mode_lib->vba.MaximumPixelsPerLinePerDSCUnit = ip->maximum_pixels_per_line_per_dsc_unit;
-	mode_lib->vba.MaxNumDP2p0Outputs = ip->max_num_dp2p0_outputs;
-	mode_lib->vba.MaxNumDP2p0Streams = ip->max_num_dp2p0_streams;
 	mode_lib->vba.DCCMetaBufferSizeBytes = ip->dcc_meta_buffer_size_bytes;
 
 	mode_lib->vba.PixelChunkSizeInKByte = ip->pixel_chunk_size_kbytes;
@@ -560,7 +557,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		mode_lib->vba.UsesMALLForPStateChange[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_pstate_change;
 		mode_lib->vba.UseMALLForStaticScreen[mode_lib->vba.NumberOfActivePlanes] = src->use_mall_for_static_screen;
 		mode_lib->vba.GPUVMMinPageSizeKBytes[mode_lib->vba.NumberOfActivePlanes] = src->gpuvm_min_page_size_kbytes;
-		mode_lib->vba.RefreshRate[mode_lib->vba.NumberOfActivePlanes] = dst->refresh_rate; //todo remove this
 		mode_lib->vba.OutputLinkDPRate[mode_lib->vba.NumberOfActivePlanes] = dout->dp_rate;
 		mode_lib->vba.ODMUse[mode_lib->vba.NumberOfActivePlanes] = dst->odm_combine_policy;
 		mode_lib->vba.DETSizeOverride[mode_lib->vba.NumberOfActivePlanes] = src->det_size_override;
@@ -606,8 +602,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		mode_lib->vba.VActive[mode_lib->vba.NumberOfActivePlanes] = dst->vactive;
 		mode_lib->vba.SurfaceTiling[mode_lib->vba.NumberOfActivePlanes] =
 				(enum dm_swizzle_mode) (src->sw_mode);
-		mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] =
-				dst->recout_width; // TODO: or should this be full_recout_width???...maybe only when in hsplit mode?
 		mode_lib->vba.ODMCombineEnabled[mode_lib->vba.NumberOfActivePlanes] =
 				dst->odm_combine;
 		mode_lib->vba.OutputFormat[mode_lib->vba.NumberOfActivePlanes] =
@@ -770,7 +764,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 		if (src->is_hsplit) {
 			for (k = j + 1; k < mode_lib->vba.cache_num_pipes; ++k) {
 				display_pipe_source_params_st *src_k = &pipes[k].pipe.src;
-				display_pipe_dest_params_st *dst_k = &pipes[k].pipe.dest;
 
 				if (src_k->is_hsplit && !visited[k]
 						&& src->hsplit_grp == src_k->hsplit_grp) {
@@ -783,8 +776,6 @@ static void fetch_pipe_params(struct display_mode_lib *mode_lib)
 								src_k->viewport_width;
 						mode_lib->vba.ViewportWidthChroma[mode_lib->vba.NumberOfActivePlanes] +=
 								src_k->viewport_width_c;
-						mode_lib->vba.ScalerRecoutWidth[mode_lib->vba.NumberOfActivePlanes] +=
-								dst_k->recout_width;
 					} else {
 						mode_lib->vba.ViewportHeight[mode_lib->vba.NumberOfActivePlanes] +=
 								src_k->viewport_height;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index a07e97035dd1..5eaedc3bf2c8 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -437,7 +437,6 @@ struct vba_vars_st {
 	unsigned int MALLAllocatedForDCNFinal;
 	double MaxAveragePercentOfIdealFabricBWDisplayCanUseInNormalSystemOperation;
 	double MaxAveragePercentOfIdealDRAMBWDisplayCanUseInNormalSystemOperationSTROBE;
-	double PercentOfIdealDRAMBWReceivedAfterUrgLatencySTROBE;
 	double WritebackLatency;
 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly; // Mode Support
 	double PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelMixedWithVMData; // Mode Support
@@ -528,7 +527,6 @@ struct vba_vars_st {
 	unsigned int MinCompressedBufferSizeInKByte;
 	unsigned int NumberOfActiveSurfaces;
 	bool ViewportStationary[DC__NUM_DPP__MAX];
-	unsigned int RefreshRate[DC__NUM_DPP__MAX];
 	double       OutputBPP[DC__NUM_DPP__MAX];
 	unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
 	bool SynchronizeTimingsFinal;
@@ -564,7 +562,6 @@ struct vba_vars_st {
 	double PixelClock[DC__NUM_DPP__MAX];
 	double PixelClockBackEnd[DC__NUM_DPP__MAX];
 	bool DCCEnable[DC__NUM_DPP__MAX];
-	bool FECEnable[DC__NUM_DPP__MAX];
 	unsigned int DCCMetaPitchY[DC__NUM_DPP__MAX];
 	unsigned int DCCMetaPitchC[DC__NUM_DPP__MAX];
 	enum scan_direction_class SourceScan[DC__NUM_DPP__MAX];
@@ -585,7 +582,6 @@ struct vba_vars_st {
 	unsigned int VActive[DC__NUM_DPP__MAX];
 	bool Interlace[DC__NUM_DPP__MAX];
 	enum dm_swizzle_mode SurfaceTiling[DC__NUM_DPP__MAX];
-	unsigned int ScalerRecoutWidth[DC__NUM_DPP__MAX];
 	bool DynamicMetadataEnable[DC__NUM_DPP__MAX];
 	int DynamicMetadataLinesBeforeActiveRequired[DC__NUM_DPP__MAX];
 	unsigned int DynamicMetadataTransmittedBytes[DC__NUM_DPP__MAX];
@@ -753,8 +749,6 @@ struct vba_vars_st {
 	bool DCCProgrammingAssumesScanDirectionUnknownFinal;
 	bool EnoughWritebackUnits;
 	bool ODMCombine2To1SupportCheckOK[DC__VOLTAGE_STATES];
-	unsigned int MaxNumDP2p0Streams;
-	unsigned int MaxNumDP2p0Outputs;
 	enum dm_output_type OutputTypePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 	enum dm_output_rate OutputRatePerState[DC__VOLTAGE_STATES][DC__NUM_DPP__MAX];
 	double WritebackLineBufferLumaBufferSize;
-- 
2.37.1

[PATCH 16/16] drm/amd/display: Remove never used VBA variables

[Maíra Canal]

The variables OutputBPP, VTotal_Min,
TotalBandwidthConsumedGBytePerSecond, BandwidthSupport,
dummy_integer_array, dummysinglestring,
SurfaceRequiredDISPCLKWithoutODMCombine, SurfaceRequiredDISPCLK,
MinVoltageLevel, and MaxVoltageLevel are never used. So, remove the
variables entries from the struct vba_vars_st.

Signed-off-by: Maíra Canal <mairacanal@riseup.net>
---
 drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
index 5eaedc3bf2c8..839f8fde4b47 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_vba.h
@@ -527,7 +527,6 @@ struct vba_vars_st {
 	unsigned int MinCompressedBufferSizeInKByte;
 	unsigned int NumberOfActiveSurfaces;
 	bool ViewportStationary[DC__NUM_DPP__MAX];
-	double       OutputBPP[DC__NUM_DPP__MAX];
 	unsigned int GPUVMMinPageSizeKBytes[DC__NUM_DPP__MAX];
 	bool SynchronizeTimingsFinal;
 	bool SynchronizeDRRDisplaysForUCLKPStateChangeFinal;
@@ -557,7 +556,6 @@ struct vba_vars_st {
 	unsigned int HTotal[DC__NUM_DPP__MAX];
 	unsigned int VTotal[DC__NUM_DPP__MAX];
 	unsigned int VTotal_Max[DC__NUM_DPP__MAX];
-	unsigned int VTotal_Min[DC__NUM_DPP__MAX];
 	int DPPPerPlane[DC__NUM_DPP__MAX];
 	double PixelClock[DC__NUM_DPP__MAX];
 	double PixelClockBackEnd[DC__NUM_DPP__MAX];
@@ -690,12 +688,10 @@ struct vba_vars_st {
 	/*outputs*/
 	bool ScaleRatioAndTapsSupport;
 	bool SourceFormatPixelAndScanSupport;
-	double TotalBandwidthConsumedGBytePerSecond;
 	bool DCCEnabledInAnyPlane;
 	bool WritebackLatencySupport;
 	bool WritebackModeSupport;
 	bool Writeback10bpc420Supported;
-	bool BandwidthSupport[DC__VOLTAGE_STATES];
 	unsigned int TotalNumberOfActiveWriteback;
 	double CriticalPoint;
 	double ReturnBWToDCNPerState;
@@ -955,9 +951,7 @@ struct vba_vars_st {
 	unsigned int        dummyinteger9;
 	unsigned int        dummyinteger10;
 	unsigned int        dummyinteger11;
-	unsigned int        dummy_integer_array[8][DC__NUM_DPP__MAX];
 
-	bool           dummysinglestring;
 	bool           SingleDPPViewportSizeSupportPerPlane[DC__NUM_DPP__MAX];
 	double         PlaneRequiredDISPCLKWithODMCombine2To1;
 	double         PlaneRequiredDISPCLKWithODMCombine4To1;
@@ -1248,11 +1242,7 @@ struct vba_vars_st {
 	unsigned int NotEnoughUrgentLatencyHidingA[DC__VOLTAGE_STATES][2];
 	double ReadBandwidthSurfaceLuma[DC__NUM_DPP__MAX];
 	double ReadBandwidthSurfaceChroma[DC__NUM_DPP__MAX];
-	double SurfaceRequiredDISPCLKWithoutODMCombine;
-	double SurfaceRequiredDISPCLK;
 	double MinActiveFCLKChangeLatencySupported;
-	int MinVoltageLevel;
-	int MaxVoltageLevel;
 	unsigned int TotalNumberOfSingleDPPSurfaces[DC__VOLTAGE_STATES][2];
 	unsigned int CompressedBufferSizeInkByteAllStates[DC__VOLTAGE_STATES][2];
 	unsigned int DETBufferSizeInKByteAllStates[DC__VOLTAGE_STATES][2][DC__NUM_DPP__MAX];
-- 
2.37.1