From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>,
Melissa Wen <mwen@igalia.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Stephen Rothwell <sfr@canb.auug.org.au>
Subject: [PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code
Date: Thu, 28 Jul 2022 16:33:47 -0400 [thread overview]
Message-ID: <20220728203347.2019728-1-Rodrigo.Siqueira@amd.com> (raw)
We got a report from Stephen/Michael that the PowerPC build was failing
with the following error:
ld: drivers/gpu/drm/amd/display/dc/dml/display_mode_lib.o uses hard float, drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o uses soft float
ld: failed to merge target specific data of file drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.o
This error happened because of the function optc3_set_vrr_m_const. This
function expects a double as a parameter in a code that is not allowed
to have FPU operations. After further investigation, it became clear
that optc3_set_vrr_m_const was never invoked, so we can safely drop this
function and fix the ld issue.
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Melissa Wen <mwen@igalia.com>
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Reported-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c | 8 --------
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h | 3 ---
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c | 1 -
drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 2 --
4 files changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
index d072997477dd..1782b9c26cf4 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.c
@@ -184,14 +184,6 @@ void optc3_set_dsc_config(struct timing_generator *optc,
REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0);
}
-void optc3_set_vrr_m_const(struct timing_generator *optc,
- double vtotal_avg)
-{
- DC_FP_START();
- optc3_fpu_set_vrr_m_const(optc, vtotal_avg);
- DC_FP_END();
-}
-
void optc3_set_odm_bypass(struct timing_generator *optc,
const struct dc_crtc_timing *dc_crtc_timing)
{
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
index 33bd12f5dc17..dd45a5499b07 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_optc.h
@@ -329,9 +329,6 @@ void optc3_lock_doublebuffer_enable(struct timing_generator *optc);
void optc3_lock_doublebuffer_disable(struct timing_generator *optc);
-void optc3_set_vrr_m_const(struct timing_generator *optc,
- double vtotal_avg);
-
void optc3_set_drr_trigger_window(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
index 992e56c6907e..eff1f4e17689 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_optc.c
@@ -281,7 +281,6 @@ static struct timing_generator_funcs dcn32_tg_funcs = {
.lock_doublebuffer_enable = optc3_lock_doublebuffer_enable,
.lock_doublebuffer_disable = optc3_lock_doublebuffer_disable,
.enable_optc_clock = optc1_enable_optc_clock,
- .set_vrr_m_const = optc3_set_vrr_m_const,
.set_drr = optc31_set_drr, // TODO: Update to optc32_set_drr once FW headers are promoted
.get_last_used_drr_vtotal = optc2_get_last_used_drr_vtotal,
.set_vtotal_min_max = optc3_set_vtotal_min_max,
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
index 62d4683f17a2..4cfa733cf96f 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h
@@ -302,8 +302,6 @@ struct timing_generator_funcs {
int group_idx,
uint32_t gsl_ready_signal);
void (*set_out_mux)(struct timing_generator *tg, enum otg_out_mux_dest dest);
- void (*set_vrr_m_const)(struct timing_generator *optc,
- double vtotal_avg);
void (*set_drr_trigger_window)(struct timing_generator *optc,
uint32_t window_start, uint32_t window_end);
void (*set_vtotal_change_limit)(struct timing_generator *optc,
--
2.35.1
next reply other threads:[~2022-07-28 20:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-28 20:33 Rodrigo Siqueira [this message]
2022-07-28 20:35 ` [PATCH] drm/amd/display: Fix a compilation failure on PowerPC caused by FPU code Alex Deucher
2022-07-28 22:48 ` Michael Ellerman
2022-07-29 12:17 ` Maíra Canal
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220728203347.2019728-1-Rodrigo.Siqueira@amd.com \
--to=rodrigo.siqueira@amd.com \
--cc=alexander.deucher@amd.com \
--cc=amd-gfx@lists.freedesktop.org \
--cc=mpe@ellerman.id.au \
--cc=mwen@igalia.com \
--cc=sfr@canb.auug.org.au \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).