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From: brichang <Brian.Chang@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: stylon.wang@amd.com, Brian Chang <Brian.Chang@amd.com>,
	Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, solomon.chiu@amd.com, Aurabindo.Pillai@amd.com,
	Alvin Lee <Alvin.Lee2@amd.com>,
	wayne.lin@amd.com, Jun Lei <Jun.Lei@amd.com>,
	Bhawanpreet.Lakha@amd.com, agustin.gutierrez@amd.com,
	pavle.kotarac@amd.com
Subject: [PATCH 10/22] drm/amd/display: Check if PSR enabled when entering MALL
Date: Fri, 18 Nov 2022 20:59:23 +0800	[thread overview]
Message-ID: <20221118125935.4013669-11-Brian.Chang@amd.com> (raw)
In-Reply-To: <20221118125935.4013669-1-Brian.Chang@amd.com>

From: Alvin Lee <Alvin.Lee2@amd.com>

[Description]
- When attempting to enter MALL SS when a PSR panel
  is connected, we have to check that the PSR panel
  has already entered PSR because the vsync interrupt
  call is per display index (can be called for the
  non-PSR panel first)
- Also don't override link settings when programming
  phantom stream (main and phantom pipe share the same link)

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
---
 .../gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c  | 9 +++++++--
 drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c       | 7 ++++++-
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
index c5380ce70653..913a1fe6b3da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
@@ -1561,8 +1561,13 @@ static enum dc_status apply_single_controller_ctx_to_hw(
 
 	pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL;
 
-	pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
-
+	/* Phantom and main stream share the same link (because the stream
+	 * is constructed with the same sink). Make sure not to override
+	 * and link programming on the main.
+	 */
+	if (pipe_ctx->stream->mall_stream_config.type != SUBVP_PHANTOM) {
+		pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
+	}
 	return DC_OK;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
index 763311ffb967..61f129faf251 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c
@@ -227,8 +227,13 @@ static uint32_t dcn32_calculate_cab_allocation(struct dc *dc, struct dc_state *c
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
 
+		/* If PSR is supported on an eDP panel that's connected, but that panel is
+		 * not in PSR at the time of trying to enter MALL SS, we have to include it
+		 * in the static screen CAB calculation
+		 */
 		if (!pipe->stream || !pipe->plane_state ||
-				pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED ||
+				(pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED &&
+				pipe->stream->link->psr_settings.psr_allow_active) ||
 				pipe->stream->mall_stream_config.type == SUBVP_PHANTOM)
 			continue;
 
-- 
2.25.1


  parent reply	other threads:[~2022-11-18 17:01 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-18 12:59 [PATCH 00/22] DC Patches November 19, 2022 brichang
2022-11-18 12:59 ` [PATCH 01/22] drm/amd/display: new ABM config 2 brichang
2022-11-18 12:59 ` [PATCH 02/22] drm/amd/display: Add margin on DRR vblank start for subvp brichang
2022-11-18 12:59 ` [PATCH 03/22] drm/amd/display: No display after resume from WB/CB brichang
2022-11-18 12:59 ` [PATCH 04/22] drm/amd/display: Limit HW cursor size of >= 4k brichang
2022-11-18 12:59 ` [PATCH 05/22] drm/amd/display: Update Z8 watermarks for DCN314 brichang
2022-11-18 12:59 ` [PATCH 06/22] drm/amd/display: Add Z8 allow states to z-state support list brichang
2022-11-18 12:59 ` [PATCH 07/22] drm/amd/display: Update soc bounding box for dcn32/dcn321 brichang
2022-11-18 12:59 ` [PATCH 08/22] drm/amd/display: Use dummy pstate latency for subvp when needed on dcn32 brichang
2022-11-18 12:59 ` [PATCH 09/22] drm/amd/display: Add check for DET fetch latency hiding for dcn32 brichang
2022-11-18 12:59 ` brichang [this message]
2022-11-18 12:59 ` [PATCH 11/22] drm/amd/display: Use viewport height for subvp mall allocation size brichang
2022-11-18 12:59 ` [PATCH 12/22] drm/amd/display: Add YCBCR2020 coefficients to CSC matrix brichang
2022-11-18 12:59 ` [PATCH 13/22] drm/amd/display: Phase 1 Add Bw Allocation source and header files brichang
2022-11-18 12:59 ` [PATCH 14/22] drm/amd/display: No display after resume from WB/CB[modify] brichang
2022-11-18 12:59 ` [PATCH 15/22] drm/amd/display: Add debug options for increasing phantom lines brichang
2022-11-18 12:59 ` [PATCH 16/22] drm/amd/display: Retain phantom plane/stream if validation fails brichang
2022-11-18 12:59 ` [PATCH 17/22] drm/amd/display: Fix display corruption w/ VSR enable brichang
2022-11-18 12:59 ` [PATCH 18/22] drm/amd/display: Avoid setting pixel rate divider to N/A brichang
2022-11-18 12:59 ` [PATCH 19/22] drm/amd/display: Use new num clk levels struct for max mclk index brichang
2022-11-18 12:59 ` [PATCH 20/22] drm/amd/display: Revert check for phantom BPP brichang
2022-11-18 12:59 ` [PATCH 21/22] drm/amd/display: Fix rotated cursor offset calculation brichang
2022-11-18 12:59 ` [PATCH 22/22] SWDEV-1 - dc: 3.2.213 brichang
2022-11-18 20:12   ` Alex Deucher
2022-11-19  1:55     ` Chang, Brian

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