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* [PATCH 00/67] DC Patches June 3, 2024
@ 2024-06-06 21:55 Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 01/67] drm/amd/display: Use TPS3 for ALPM on Specific Panel Zaeem Mohamed
                   ` (66 more replies)
  0 siblings, 67 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed, Daniel Wheeler

This DC patchset brings improvements in multiple areas. In summary, we have:

* FW Release 0.0.221.0
* Fixed missing targets in FAMS2
* Populate hardware_release hook for dcn401
* Disable DMCUB timeout for DCN35
* Move PRIMARY plane zpos higher
* Introduce overlay cursor mode
* Change dram_clock_latency for dcn35 and dcn351
* DCN401 cursor code update

Cc: Daniel Wheeler <daniel.wheeler@amd.com>

Alex Hung (6):
  drm/amd/display: Fix incorrect size calculation for loop in dcn401
  drm/amd/display: Fix uninitialized variables in dcn401
  drm/amd/display: Remove useless comparison of unsigned int vs. 0
  drm/amd/display: Remove NO_EFFECT self-assignment
  drm/amd/display: Explicitly cast v_total to signed in a subtraction
  drm/amd/display: Avoid overflow from uint32_t to uint8_t

Alvin Lee (3):
  drm/amd/display: Remove NULL assignment for stream_status
  drm/amd/display: Ignore phantom DTBCLK requirement
  drm/amd/display: populate hardware_release hook for dcn401

Anthony Koo (2):
  drm/amd/display: [FW Promotion] Release 0.0.220.0
  drm/amd/display: [FW Promotion] Release 0.0.221.0

Aric Cyr (1):
  drm/amd/display: 3.2.288

Chris Park (3):
  drm/amd/display: Change AVI Info Frame version to 4 for OVT
  drm/amd/display: Prevent overflow on DTO calculation
  drm/amd/display: Avoid programming DTO if Refclk is 0

ChunTao Tso (2):
  drm/amd/display: Replay low hz
  drm/amd/display: Replay + IPS + ABM in Full Screen VPB

Daniel Miess (2):
  drm/amd/display: Change dram_clock_latency to 34us for dcn351
  drm/amd/display: Disable PHYSYMCLK RCO

Daniel Sa (1):
  drm/amd/display: Return after Init

Dennis Chan (1):
  drm/amd/display: Fix Replay Desync Error Test

Dillon Varone (5):
  drm/amd/display: Block SubVP if hardware rotation is used in DML2.1
  drm/amd/display: Add null check for phantom pipes in prepare mcache
  drm/amd/display: Fix missed targets in FAMS2+HWFQ
  drm/amd/display: Do not override dml2.1 reinit
  drm/amd/display: Update idle hardmins if uclk or fclk requirement
    changed

Fangzhi Zuo (1):
  drm/amd/display: Update efficiency bandwidth for dcn351

George Shen (1):
  drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max
    link rate

Ivan Lipski (5):
  drm/amd/display: Remove redundant if conditions
  drm/amd/display: Remove unreachable check
  drm/amd/display: Remove redundant ternary operation
  drm/amd/display: Remove duplicate 'update_idle_uclk' in dcn401 clk_mgr
    code
  drm/amd/display: Remove reduntant comparisons by Coverity

JinZe.Xu (1):
  drm/amd/display: Disable IPS when it is not allowed.

Joshua Aberback (1):
  drm/amd/display: Disable boot optimization for DCN401

Josip Pavic (1):
  drm/amd/display: define abm debug interface

Leo Li (2):
  drm/amd/display: Introduce overlay cursor mode
  drm/amd/display: Move PRIMARY plane zpos higher

Leon Huang (1):
  drm/amd/display: Expand supported Replay residency mode

Michael Strauss (2):
  drm/amd/display: Update FIXED_VS retimer training pattern delay
  drm/amd/display: Add fallback defaults for invalid LTTPR DPCD caps

Nevenko Stupar (1):
  drm/amd/display: Fix multiple cursors when using 4 displays on a
    contiguous large surface

Nicholas Kazlauskas (3):
  drm/amd/display: Add sequential ONO sequencing for DCN35
  drm/amd/display: Remove register from DCN35 DMCUB diagnostic
    collection
  drm/amd/display: Disable DMCUB timeout for DCN35

Paul Hsieh (1):
  drm/amd/display: change dram_clock_latency to 34us for dcn35

Rodrigo Siqueira (2):
  drm/amd/display: Use the SPDX license identifier for dmub_replay files
  drm/amd/display: Check otg_master pointer before use it

Roman Li (1):
  drm/amd/display: Add config support entry to replay caps debugfs

Sridevi Arvindekar (2):
  drm/amd/display: DCN401 cusor code update
  drm/amd/display: Minor cleanup for DCN401 cursor related code

Sung-huai Wang (1):
  Revert "drm/amd/display: Handle HPD_IRQ for internal link"

Wayne Lin (5):
  drm/amd/display: Adjust debug msg for usb4/tbt
  drm/amd/display: Defer the setting of link hpd status for usb4/tbt
  drm/amd/display: Correct the defined value for
    AMDGPU_DMUB_NOTIFICATION_MAX
  drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_compute
  drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()

Wenjing Liu (7):
  drm/amd/display: use even ODM slice width for two pixels per container
  drm/amd/display: add odm_slice_rect parameter in spl_in
  drm/amd/display: reduce ODM slice count to initial new dc state only
    when needed
  drm/amd/display: remove dpp pipes on failure to update pipe params
  drm/amd/display: remove ODM combine before bandwidth validation
  drm/amd/display: use preferred link settings for dp signal only
  drm/amd/display: make ODM segment width of YCbCr422 two pixel aligned

Zaeem Mohamed (1):
  drm/amd/display: Remove dcn32_smu13 duplicate header

pochchan (1):
  drm/amd/display: Use TPS3 for ALPM on Specific Panel

winstang (1):
  drm/amd/display: added NULL check at start of dc_validate_stream

 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 589 +++++++++++++-----
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   9 +-
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c |   1 +
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 248 +++++---
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  29 +-
 .../drm/amd/display/dc/basics/fixpt31_32.c    |   4 -
 .../amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |   8 +-
 .../display/dc/clk_mgr/dcn301/vg_clk_mgr.c    |   8 +-
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  |   2 +-
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c  |   2 +-
 .../dc/clk_mgr/dcn32/smu13_driver_if.h        | 108 ----
 .../dc/clk_mgr/dcn401/dcn401_clk_mgr.c        |   2 +-
 .../gpu/drm/amd/display/dc/core/dc_resource.c |  90 ++-
 .../gpu/drm/amd/display/dc/core/dc_state.c    |  67 +-
 .../gpu/drm/amd/display/dc/core/dc_stream.c   |   4 +-
 drivers/gpu/drm/amd/display/dc/dc.h           |   4 +-
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c  |   5 +-
 .../gpu/drm/amd/display/dc/dc_spl_translate.c |   5 +-
 .../amd/display/dc/dccg/dcn401/dcn401_dccg.c  |   6 +-
 .../drm/amd/display/dc/dce/dce_clock_source.c |  12 +-
 .../drm/amd/display/dc/dce/dce_mem_input.c    |   6 +-
 .../gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c |   2 +-
 .../gpu/drm/amd/display/dc/dce/dmub_replay.c  | 124 ++--
 .../gpu/drm/amd/display/dc/dce/dmub_replay.h  |  35 +-
 .../drm/amd/display/dc/dcn35/dcn35_pg_cntl.c  |   6 +-
 .../drm/amd/display/dc/dml/dcn32/dcn32_fpu.c  |   2 +
 .../drm/amd/display/dc/dml/dcn35/dcn35_fpu.c  |   2 +-
 .../amd/display/dc/dml/dcn351/dcn351_fpu.c    |   2 +-
 .../amd/display/dc/dml2/dml21/dml21_wrapper.c |  10 +-
 .../src/dml2_core/dml2_core_dcn4_calcs.c      |  14 +-
 .../dml21/src/dml2_core/dml2_core_shared.c    |   4 -
 .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c  |   3 +-
 .../display/dc/dml2/dml2_translation_helper.c |   1 +
 .../drm/amd/display/dc/dml2/dml2_wrapper.c    |   4 +-
 .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c  |   5 -
 .../amd/display/dc/dpp/dcn401/dcn401_dpp.c    |   5 -
 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c  |  11 +-
 .../gpu/drm/amd/display/dc/gpio/hw_generic.c  |   2 +-
 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c  |   2 +-
 .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c   |   5 +
 .../amd/display/dc/hwss/dcn21/dcn21_hwseq.c   |   2 +-
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   |  85 ++-
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c |  85 ++-
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h |   2 +-
 .../amd/display/dc/hwss/dcn401/dcn401_init.c  |   2 +-
 .../gpu/drm/amd/display/dc/irq/irq_service.c  |   2 +-
 .../link_hwss_hpo_fixed_vs_pe_retimer_dp.c    |   6 +-
 .../dc/link/protocols/link_dp_capability.c    |  46 +-
 .../dc/link/protocols/link_dp_irq_handler.c   |  24 +-
 .../dc/link/protocols/link_dp_training.c      |   8 +-
 .../dc/resource/dcn20/dcn20_resource.c        |   4 +-
 .../dc/resource/dcn30/dcn30_resource.c        |   3 -
 .../dc/resource/dcn35/dcn35_resource.c        |   7 +-
 .../dc/resource/dcn351/dcn351_resource.c      |   2 +-
 .../dc/resource/dcn401/dcn401_resource.c      |   1 +
 drivers/gpu/drm/amd/display/dc/spl/dc_spl.c   |  32 +-
 .../gpu/drm/amd/display/dc/spl/dc_spl_types.h |   4 +-
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 157 ++++-
 .../gpu/drm/amd/display/dmub/src/dmub_dcn35.c |   5 +-
 60 files changed, 1226 insertions(+), 700 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h

-- 
2.34.1


^ permalink raw reply	[flat|nested] 68+ messages in thread

* [PATCH 01/67] drm/amd/display: Use TPS3 for ALPM on Specific Panel
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 02/67] drm/amd/display: Replay low hz Zaeem Mohamed
                   ` (65 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, pochchan

From: pochchan <pochchan@amd.com>

For some specific panel, it need to use TPS3 rather than use TP2 in ALPM
when DSC is enabled.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: pochchan <pochchan@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 318d0dc113e6..b9769181269d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -33,6 +33,9 @@
 
 #define MAX_PIPES 6
 
+static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3};
+static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5};
+
 /*
  * Get Replay state from firmware.
  */
@@ -194,11 +197,11 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
 		(link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT &&
 		!link->panel_config.dsc.disable_dsc_edp &&
 		link->dc->caps.edp_dsc_support)) &&
-		link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 /*&&
+		link->dpcd_caps.sink_dev_id == DP_DEVICE_ID_38EC11 &&
 		(!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_1,
 			sizeof(DP_SINK_DEVICE_STR_ID_1)) ||
 		!memcmp(link->dpcd_caps.sink_dev_id_str, DP_SINK_DEVICE_STR_ID_2,
-			sizeof(DP_SINK_DEVICE_STR_ID_2)))*/)
+			sizeof(DP_SINK_DEVICE_STR_ID_2))))
 		copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 1;
 	else
 		copy_settings_data->flags.bitfields.force_wakeup_by_tps3 = 0;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 02/67] drm/amd/display: Replay low hz
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 01/67] drm/amd/display: Use TPS3 for ALPM on Specific Panel Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 03/67] drm/amd/display: Expand supported Replay residency mode Zaeem Mohamed
                   ` (64 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, ChunTao Tso

From: ChunTao Tso <ChunTao.Tso@amd.com>

[Why]
The original coasting vtotal is 2 bytes, and it need to be amended to 4
bytes because low hz case.

[How]
Amend coasting vtotal from 2 bytes to 4 bytes.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dmub_replay.c  | 34 +++++++++++--------
 .../gpu/drm/amd/display/dc/dce/dmub_replay.h  |  4 +--
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   |  8 +++++
 3 files changed, 30 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index b9769181269d..fd91445d4d8e 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -216,17 +216,21 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
  * Set coasting vtotal.
  */
 static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
-		uint16_t coasting_vtotal,
+		uint32_t coasting_vtotal,
 		uint8_t panel_inst)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
+	struct dmub_rb_cmd_replay_set_coasting_vtotal *pCmd = NULL;
+
+	pCmd = &(cmd.replay_set_coasting_vtotal);
 
 	memset(&cmd, 0, sizeof(cmd));
-	cmd.replay_set_coasting_vtotal.header.type = DMUB_CMD__REPLAY;
-	cmd.replay_set_coasting_vtotal.header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;
-	cmd.replay_set_coasting_vtotal.header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
-	cmd.replay_set_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;
+	pCmd->header.type = DMUB_CMD__REPLAY;
+	pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;
+	pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
+	pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
+	pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
 
 	dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 }
@@ -259,20 +263,22 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,
  * Set REPLAY power optimization flags and coasting vtotal.
  */
 static void dmub_replay_set_power_opt_and_coasting_vtotal(struct dmub_replay *dmub,
-		unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal)
+		unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal)
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = dmub->ctx;
+	struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal *pCmd = NULL;
+
+	pCmd = &(cmd.replay_set_power_opt_and_coasting_vtotal);
 
 	memset(&cmd, 0, sizeof(cmd));
-	cmd.replay_set_power_opt_and_coasting_vtotal.header.type = DMUB_CMD__REPLAY;
-	cmd.replay_set_power_opt_and_coasting_vtotal.header.sub_type =
-		DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;
-	cmd.replay_set_power_opt_and_coasting_vtotal.header.payload_bytes =
-		sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal);
-	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.power_opt = power_opt;
-	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_power_opt_data.panel_inst = panel_inst;
-	cmd.replay_set_power_opt_and_coasting_vtotal.replay_set_coasting_vtotal_data.coasting_vtotal = coasting_vtotal;
+	pCmd->header.type = DMUB_CMD__REPLAY;
+	pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_POWER_OPT_AND_COASTING_VTOTAL;
+	pCmd->header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_set_power_opt_and_coasting_vtotal);
+	pCmd->replay_set_power_opt_data.power_opt = power_opt;
+	pCmd->replay_set_power_opt_data.panel_inst = panel_inst;
+	pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
+	pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
 
 	dc_wake_and_execute_dmub_cmd(dc, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
index 3613aff994d7..d090ec900c08 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
@@ -47,12 +47,12 @@ struct dmub_replay_funcs {
 		uint8_t panel_inst);
 	void (*replay_send_cmd)(struct dmub_replay *dmub,
 		enum replay_FW_Message_type msg, union dmub_replay_cmd_set *cmd_element);
-	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint16_t coasting_vtotal,
+	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,
 		uint8_t panel_inst);
 	void (*replay_residency)(struct dmub_replay *dmub,
 		uint8_t panel_inst, uint32_t *residency, const bool is_start, const bool is_alpm);
 	void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,
-		unsigned int power_opt, uint8_t panel_inst, uint16_t coasting_vtotal);
+		unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal);
 };
 
 struct dmub_replay *dmub_replay_create(struct dc_context *ctx);
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 36c15ae43616..fe529b67369e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -3004,6 +3004,14 @@ struct dmub_cmd_update_dirty_rect_data {
 	 * Currently the support is only for 0 or 1
 	 */
 	uint8_t panel_inst;
+	/**
+	 * 16-bit value dicated by driver that indicates the coasting vtotal high byte part.
+	 */
+	uint16_t coasting_vtotal_high;
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad[2];
 };
 
 /**
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 03/67] drm/amd/display: Expand supported Replay residency mode
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 01/67] drm/amd/display: Use TPS3 for ALPM on Specific Panel Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 02/67] drm/amd/display: Replay low hz Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 04/67] drm/amd/display: Replay + IPS + ABM in Full Screen VPB Zaeem Mohamed
                   ` (63 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Leon Huang, Rodrigo Siqueira

From: Leon Huang <Leon.Huang1@amd.com>

[Why]
Dmub provides several Replay residency calculation methods, but current
interface only supports either ALPM or PHY mode

[How]
Modify the interface for supporting different types of Replay residency
calculation.

Reviewed-by: Rodrigo Siqueira <Rodrigo Siqueira@amd.com>
Signed-off-by: Leon Huang <Leon.Huang1@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dmub_replay.c  | 32 ++++++++++++++-----
 .../gpu/drm/amd/display/dc/dce/dmub_replay.h  |  2 +-
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index fd91445d4d8e..be27ab7ef2da 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -239,23 +239,39 @@ static void dmub_replay_set_coasting_vtotal(struct dmub_replay *dmub,
  * Get Replay residency from firmware.
  */
 static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst,
-	uint32_t *residency, const bool is_start, const bool is_alpm)
+	uint32_t *residency, const bool is_start, enum pr_residency_mode mode)
 {
-	struct dmub_srv *srv = dmub->ctx->dmub_srv->dmub;
 	uint16_t param = (uint16_t)(panel_inst << 8);
 
-	if (is_alpm)
+	switch (mode) {
+	case PR_RESIDENCY_MODE_PHY:
+		param |= REPLAY_RESIDENCY_FIELD_MODE_PHY;
+		break;
+	case PR_RESIDENCY_MODE_ALPM:
 		param |= REPLAY_RESIDENCY_FIELD_MODE_ALPM;
+		break;
+	case PR_RESIDENCY_MODE_IPS2:
+		param |= REPLAY_RESIDENCY_REVISION_1;
+		param |= REPLAY_RESIDENCY_FIELD_MODE2_IPS;
+		break;
+	case PR_RESIDENCY_MODE_FRAME_CNT:
+		param |= REPLAY_RESIDENCY_REVISION_1;
+		param |= REPLAY_RESIDENCY_FIELD_MODE2_FRAME_CNT;
+		break;
+	case PR_RESIDENCY_MODE_ENABLEMENT_PERIOD:
+		param |= REPLAY_RESIDENCY_REVISION_1;
+		param |= REPLAY_RESIDENCY_FIELD_MODE2_EN_PERIOD;
+		break;
+	default:
+		break;
+	}
 
 	if (is_start)
 		param |= REPLAY_RESIDENCY_ENABLE;
 
 	// Send gpint command and wait for ack
-	dmub_srv_send_gpint_command(srv, DMUB_GPINT__REPLAY_RESIDENCY, param, 30);
-
-	if (!is_start)
-		dmub_srv_get_gpint_response(srv, residency);
-	else
+	if (!dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__REPLAY_RESIDENCY, param,
+				       residency, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
 		*residency = 0;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
index d090ec900c08..63bbb1bb0ad5 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
@@ -50,7 +50,7 @@ struct dmub_replay_funcs {
 	void (*replay_set_coasting_vtotal)(struct dmub_replay *dmub, uint32_t coasting_vtotal,
 		uint8_t panel_inst);
 	void (*replay_residency)(struct dmub_replay *dmub,
-		uint8_t panel_inst, uint32_t *residency, const bool is_start, const bool is_alpm);
+		uint8_t panel_inst, uint32_t *residency, const bool is_start, const enum pr_residency_mode mode);
 	void (*replay_set_power_opt_and_coasting_vtotal)(struct dmub_replay *dmub,
 		unsigned int power_opt, uint8_t panel_inst, uint32_t coasting_vtotal);
 };
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 04/67] drm/amd/display: Replay + IPS + ABM in Full Screen VPB
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (2 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 03/67] drm/amd/display: Expand supported Replay residency mode Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 05/67] drm/amd/display: Fix Replay Desync Error Test Zaeem Mohamed
                   ` (62 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, ChunTao Tso

From: ChunTao Tso <ChunTao.Tso@amd.com>

[Why]
Because ABM will wait VStart to start getting histogram data, it will
cause we can't enter IPS while full screnn video playing.

[How]
Modify the panel refresh rate to the maximun multiple of current refresh
rate

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: ChunTao Tso <ChunTao.Tso@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index be27ab7ef2da..958a927d0cea 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -350,6 +350,18 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub,
 		cmd.replay_set_frameupdate_timer.data.frameupdate_count =
 						cmd_element->timer_data.frameupdate_count;
 		break;
+	case Replay_Set_Pseudo_VTotal:
+		//Header
+		cmd.replay_set_pseudo_vtotal.header.sub_type =
+			DMUB_CMD__REPLAY_SET_PSEUDO_VTOTAL;
+		cmd.replay_set_pseudo_vtotal.header.payload_bytes =
+			sizeof(struct dmub_rb_cmd_replay_set_pseudo_vtotal);
+		//Cmd Body
+		cmd.replay_set_pseudo_vtotal.data.panel_inst =
+			cmd_element->pseudo_vtotal_data.panel_inst;
+		cmd.replay_set_pseudo_vtotal.data.vtotal =
+			cmd_element->pseudo_vtotal_data.vtotal;
+		break;
 	case Replay_Msg_Not_Support:
 	default:
 		return;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 05/67] drm/amd/display: Fix Replay Desync Error Test
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (3 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 04/67] drm/amd/display: Replay + IPS + ABM in Full Screen VPB Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 06/67] drm/amd/display: use even ODM slice width for two pixels per container Zaeem Mohamed
                   ` (61 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Dennis Chan

From: Dennis Chan <dennis.chan@amd.com>

When PHY power off, the DP_SEC_CNTL cannot be configured and cause
disable Adaptive sync SDP failed. Regarding the issue, the driver will
disabled AS-SDP in replay state machine.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Dennis Chan <dennis.chan@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 958a927d0cea..62e03fdf813b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -362,6 +362,18 @@ static void dmub_replay_send_cmd(struct dmub_replay *dmub,
 		cmd.replay_set_pseudo_vtotal.data.vtotal =
 			cmd_element->pseudo_vtotal_data.vtotal;
 		break;
+	case Replay_Disabled_Adaptive_Sync_SDP:
+		//Header
+		cmd.replay_disabled_adaptive_sync_sdp.header.sub_type =
+			DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP;
+		cmd.replay_disabled_adaptive_sync_sdp.header.payload_bytes =
+			sizeof(struct dmub_rb_cmd_replay_set_pseudo_vtotal);
+		//Cmd Body
+		cmd.replay_disabled_adaptive_sync_sdp.data.panel_inst =
+			cmd_element->disabled_adaptive_sync_sdp_data.panel_inst;
+		cmd.replay_disabled_adaptive_sync_sdp.data.force_disabled =
+			cmd_element->disabled_adaptive_sync_sdp_data.force_disabled;
+		break;
 	case Replay_Msg_Not_Support:
 	default:
 		return;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 06/67] drm/amd/display: use even ODM slice width for two pixels per container
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (4 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 05/67] drm/amd/display: Fix Replay Desync Error Test Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 07/67] drm/amd/display: add odm_slice_rect parameter in spl_in Zaeem Mohamed
                   ` (60 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
When optc uses two pixel per container, each ODM slice width must be an
even number.

[how]
If ODM slice width is odd number increase it by 1.

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/spl/dc_spl.c       | 3 +++
 drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h | 1 +
 2 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
index 2836f28fa3af..9c6171e90163 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
@@ -173,6 +173,9 @@ static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_i
 	int odm_slice_width = h_active / odm_slice_count;
 	struct spl_rect odm_rec;
 
+	if (spl_in->basic_out.use_two_pixels_per_container && (odm_slice_width % 2))
+		odm_slice_width++;
+
 	odm_rec.x = odm_slice_width * odm_slice_idx;
 	odm_rec.width = is_last_odm_slice ?
 			/* last slice width is the reminder of h_active */
diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
index a8f7fccfa16b..49c866a558f6 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
@@ -441,6 +441,7 @@ struct basic_out {
 	bool always_scale;	// Is always scale enabled? Required for getting SCL_MODE
 	int max_downscale_src_width; // Required to get optimal no of taps
 	bool alpha_en;
+	bool use_two_pixels_per_container;
 };
 enum explicit_sharpness	{
 	SHARPNESS_LOW = 0,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 07/67] drm/amd/display: add odm_slice_rect parameter in spl_in
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (5 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 06/67] drm/amd/display: use even ODM slice width for two pixels per container Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 08/67] drm/amd/display: Remove redundant if conditions Zaeem Mohamed
                   ` (59 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
OPP input rect aka odm slice rect is a hardware dependent parameter that
can't be determined by SPL software logic. Therefore we need to
explicitly pass odm slice rect in. So ODM slice rect calculation is
moved out of SPL.

[how]
add odm_slice_rect parameter in spl_in

Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 .../gpu/drm/amd/display/dc/dc_spl_translate.c |  5 ++-
 drivers/gpu/drm/amd/display/dc/spl/dc_spl.c   | 35 ++++++++++++-------
 .../gpu/drm/amd/display/dc/spl/dc_spl_types.h |  3 +-
 3 files changed, 28 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
index bc760448a378..582606319764 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c
@@ -70,6 +70,8 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
 {
 	const struct dc_plane_state *plane_state = pipe_ctx->plane_state;
 	const struct dc_stream_state *stream = pipe_ctx->stream;
+	struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx);
+
 	// Assign the function to calculate the number of partitions in the line buffer
 	// This is used to determine the vtap support
 	switch (plane_state->ctx->dce_version)	{
@@ -112,7 +114,8 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl
 	else
 		spl_in->basic_in.mpc_combine_v = resource_get_mpc_slice_index(pipe_ctx);
 
-	spl_in->basic_out.odm_combine_factor = resource_get_odm_slice_count(pipe_ctx);
+	populate_splrect_from_rect(&spl_in->basic_out.odm_slice_rect, &odm_slice_src);
+	spl_in->basic_out.odm_combine_factor = 0;
 	spl_in->odm_slice_index = resource_get_odm_slice_index(pipe_ctx);
 	// Make spl input basic out info output_size width point to stream h active
 	spl_in->basic_out.output_size.width =
diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
index 9c6171e90163..ac58991eebbc 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c
@@ -170,22 +170,31 @@ static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_i
 	bool is_last_odm_slice = (odm_slice_idx + 1) == odm_slice_count;
 	int h_active = spl_in->basic_out.output_size.width;
 	int v_active = spl_in->basic_out.output_size.height;
-	int odm_slice_width = h_active / odm_slice_count;
+	int odm_slice_width;
 	struct spl_rect odm_rec;
 
-	if (spl_in->basic_out.use_two_pixels_per_container && (odm_slice_width % 2))
-		odm_slice_width++;
-
-	odm_rec.x = odm_slice_width * odm_slice_idx;
-	odm_rec.width = is_last_odm_slice ?
-			/* last slice width is the reminder of h_active */
-			h_active - odm_slice_width * (odm_slice_count - 1) :
-			/* odm slice width is the floor of h_active / count */
-			odm_slice_width;
-	odm_rec.y = 0;
-	odm_rec.height = v_active;
+	if (spl_in->basic_out.odm_combine_factor > 0) {
+		odm_slice_width = h_active / odm_slice_count;
+		/*
+		 * deprecated, caller must pass in odm slice rect i.e OPP input
+		 * rect in timing active for the new interface.
+		 */
+		if (spl_in->basic_out.use_two_pixels_per_container && (odm_slice_width % 2))
+			odm_slice_width++;
+
+		odm_rec.x = odm_slice_width * odm_slice_idx;
+		odm_rec.width = is_last_odm_slice ?
+				/* last slice width is the reminder of h_active */
+				h_active - odm_slice_width * (odm_slice_count - 1) :
+				/* odm slice width is the floor of h_active / count */
+				odm_slice_width;
+		odm_rec.y = 0;
+		odm_rec.height = v_active;
+
+		return odm_rec;
+	}
 
-	return odm_rec;
+	return spl_in->basic_out.odm_slice_rect;
 }
 
 static void spl_calculate_recout(struct spl_in *spl_in, struct spl_out *spl_out)
diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
index 49c866a558f6..201201d3f55b 100644
--- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
+++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h
@@ -436,7 +436,8 @@ struct basic_out {
 	struct spl_size output_size; // Output Size
 	struct spl_rect dst_rect;	// Destination Rect
 	struct spl_rect src_rect;	// Source rect
-	int odm_combine_factor;	// ODM Combine Factor determine by get_odm_splits
+	int odm_combine_factor;	// deprecated
+	struct spl_rect odm_slice_rect; // OPP input rect in timing active
 	enum spl_view_3d view_format;	// TODO: View format Check if it is chroma subsampling
 	bool always_scale;	// Is always scale enabled? Required for getting SCL_MODE
 	int max_downscale_src_width; // Required to get optimal no of taps
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 08/67] drm/amd/display: Remove redundant if conditions
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (6 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 07/67] drm/amd/display: add odm_slice_rect parameter in spl_in Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 09/67] drm/amd/display: Remove unreachable check Zaeem Mohamed
                   ` (58 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Ivan Lipski, Zaeem Mohamed

From: Ivan Lipski <ivlipski@amd.com>

[WHY]
Coverity analysis flagged the two if conditions in
dcn30_dpp.c and dcn401_dpp.c as DEADCODE since they
are never true, since the variable
'program_prealpha_dealpha' is initialized at 0 and
never chagnes.

[HOW]
Removed the variable 'program_prealpha_dealpha' and
the if conditions.

Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Ivan Lipski <ivlipski@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c   | 5 -----
 drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c | 5 -----
 2 files changed, 10 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
index abdf6a132e66..40acebd13e46 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
@@ -219,7 +219,6 @@ void dpp3_cnv_setup (
 	uint32_t alpha_plane_enable = 0;
 	uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
 	uint32_t realpha_en = 0, realpha_ablnd_en = 0;
-	uint32_t program_prealpha_dealpha = 0;
 	struct out_csc_color_matrix tbl_entry;
 	int i;
 
@@ -347,10 +346,6 @@ void dpp3_cnv_setup (
 			CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 
-	if (program_prealpha_dealpha) {
-		dealpha_en = 1;
-		realpha_en = 1;
-	}
 	REG_SET_2(PRE_DEALPHA, 0,
 			PRE_DEALPHA_EN, dealpha_en,
 			PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
index eee64d8e1013..7cae18fd7be9 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
@@ -68,7 +68,6 @@ void dpp401_dpp_setup(
 	uint32_t alpha_plane_enable = 0;
 	uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
 	uint32_t realpha_en = 0, realpha_ablnd_en = 0;
-	uint32_t program_prealpha_dealpha = 0;
 	struct out_csc_color_matrix tbl_entry;
 	int i;
 
@@ -192,10 +191,6 @@ void dpp401_dpp_setup(
 		CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
 	REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
 
-	if (program_prealpha_dealpha) {
-		dealpha_en = 1;
-		realpha_en = 1;
-	}
 	REG_SET_2(PRE_DEALPHA, 0,
 		PRE_DEALPHA_EN, dealpha_en,
 		PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 09/67] drm/amd/display: Remove unreachable check
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (7 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 08/67] drm/amd/display: Remove redundant if conditions Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 10/67] drm/amd/display: Remove redundant ternary operation Zaeem Mohamed
                   ` (57 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Ivan Lipski, Zaeem Mohamed

From: Ivan Lipski <ivlipski@amd.com>

[WHY]
Coverity analysis flagged this code as DEADCODE
since the condition and return in the outer loop
are never reached.

All operations with the 'dwb_pipe' variable happen
in the inner loop, that already contains the same
check with the 'MAX_DWB_PIPES'. The later
check condition cannot occur before the check
condition in the inner loop, thus the later
condition is unreacable.

[HOW]
Remove the unreachable condition.

Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Ivan Lipski <ivlipski@amd.com>
---
 drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 --
 drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c | 3 ---
 2 files changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index c78675f8be8a..b2d79c908ec2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1666,8 +1666,6 @@ void dcn20_set_mcif_arb_params(
 			if (dwb_pipe >= MAX_DWB_PIPES)
 				return;
 		}
-		if (dwb_pipe >= MAX_DWB_PIPES)
-			return;
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index 0cb2cc56d973..5040a4c6ed18 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -1419,10 +1419,7 @@ void dcn30_set_mcif_arb_params(
 			if (dwb_pipe >= MAX_DWB_PIPES)
 				return;
 		}
-		if (dwb_pipe >= MAX_DWB_PIPES)
-			return;
 	}
-
 }
 
 static struct dc_cap_funcs cap_funcs = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 10/67] drm/amd/display: Remove redundant ternary operation
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (8 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 09/67] drm/amd/display: Remove unreachable check Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 11/67] drm/amd/display: Remove dcn32_smu13 duplicate header Zaeem Mohamed
                   ` (56 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Ivan Lipski

From: Ivan Lipski <ivlipski@amd.com>

[WHY]
Coverity analysis flagged this ternary operation as
DEADCODE.

Since 'total_y_free_entry' is initialized as 0x200 and
'total_c_free_entry' is initialized as 0x140, and they
never change values before the ternary operator, so
'total_y_free_entry' is always greater 'total_c_free_entry',
'so small_free_entry' is always set to 'total_c_free_entry'.

[HOW]
Replace the ternary operator with the variable declaration.

Signed-off-by: Ivan Lipski <ivlipski@amd.com>
---
 drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index b2d79c908ec2..f93853d434d2 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1612,7 +1612,7 @@ unsigned int dcn20_calc_max_scaled_time(
 	if (time_per_byte == 0)
 		time_per_byte = 1;
 
-	small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
+	small_free_entry  = total_c_free_entry;
 	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
 	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
 	max_scaled_time   = buf_lh_capability - urgent_watermark;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 11/67] drm/amd/display: Remove dcn32_smu13 duplicate header
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (9 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 10/67] drm/amd/display: Remove redundant ternary operation Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 12/67] drm/amd/display: Remove NULL assignment for stream_status Zaeem Mohamed
                   ` (55 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

[WHY]
Duplicate headers requiring unecessary maintenance of both headers

[HOW]
Removal of smu13_driver_if header and all referneces to it changed to dcn32_smu13_driver

Signed-off-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
---
 .../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c  |   2 +-
 .../dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c  |   2 +-
 .../dc/clk_mgr/dcn32/smu13_driver_if.h        | 108 ------------------
 3 files changed, 2 insertions(+), 110 deletions(-)
 delete mode 100644 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index ff5fdc7b1198..ee4b02c8c807 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -36,7 +36,7 @@
 #include "link.h"
 #include "dc_state_priv.h"
 #include "atomfirmware.h"
-#include "smu13_driver_if.h"
+#include "dcn32_smu13_driver_if.h"
 
 #include "dcn/dcn_3_2_0_offset.h"
 #include "dcn/dcn_3_2_0_sh_mask.h"
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
index f2f60478b1a6..cf2d35363e8b 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.c
@@ -28,7 +28,7 @@
 #include "clk_mgr_internal.h"
 #include "reg_helper.h"
 #include "dalsmc.h"
-#include "smu13_driver_if.h"
+#include "dcn32_smu13_driver_if.h"
 
 #define mmDAL_MSG_REG  0x1628A
 #define mmDAL_ARG_REG  0x16273
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
deleted file mode 100644
index deeb85047e7b..000000000000
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/smu13_driver_if.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright 2021 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-#ifndef SMU13_DRIVER_IF_DCN32_H
-#define SMU13_DRIVER_IF_DCN32_H
-
-// *** IMPORTANT ***
-// PMFW TEAM: Always increment the interface version on any change to this file
-#define SMU13_DRIVER_IF_VERSION  0x18
-
-//Only Clks that have DPM descriptors are listed here
-typedef enum {
-  PPCLK_GFXCLK = 0,
-  PPCLK_SOCCLK,
-  PPCLK_UCLK,
-  PPCLK_FCLK,
-  PPCLK_DCLK_0,
-  PPCLK_VCLK_0,
-  PPCLK_DCLK_1,
-  PPCLK_VCLK_1,
-  PPCLK_DISPCLK,
-  PPCLK_DPPCLK,
-  PPCLK_DPREFCLK,
-  PPCLK_DCFCLK,
-  PPCLK_DTBCLK,
-  PPCLK_COUNT,
-} PPCLK_e;
-
-typedef enum {
-  UCLK_DIV_BY_1 = 0,
-  UCLK_DIV_BY_2,
-  UCLK_DIV_BY_4,
-  UCLK_DIV_BY_8,
-} UCLK_DIV_e;
-
-typedef struct {
-  uint8_t  WmSetting;
-  uint8_t  Flags;
-  uint8_t  Padding[2];
-
-} WatermarkRowGeneric_t;
-
-#define NUM_WM_RANGES 4
-
-typedef enum {
-  WATERMARKS_CLOCK_RANGE = 0,
-  WATERMARKS_DUMMY_PSTATE,
-  WATERMARKS_MALL,
-  WATERMARKS_COUNT,
-} WATERMARKS_FLAGS_e;
-
-typedef struct {
-  // Watermarks
-  WatermarkRowGeneric_t WatermarkRow[NUM_WM_RANGES];
-} Watermarks_t;
-
-typedef struct {
-  Watermarks_t Watermarks;
-  uint32_t  Spare[16];
-
-  uint32_t     MmHubPadding[8]; // SMU internal use
-} WatermarksExternal_t;
-
-// These defines are used with the following messages:
-// SMC_MSG_TransferTableDram2Smu
-// SMC_MSG_TransferTableSmu2Dram
-
-// Table transfer status
-#define TABLE_TRANSFER_OK         0x0
-#define TABLE_TRANSFER_FAILED     0xFF
-#define TABLE_TRANSFER_PENDING    0xAB
-
-// Table types
-#define TABLE_PMFW_PPTABLE            0
-#define TABLE_COMBO_PPTABLE           1
-#define TABLE_WATERMARKS              2
-#define TABLE_AVFS_PSM_DEBUG          3
-#define TABLE_PMSTATUSLOG             4
-#define TABLE_SMU_METRICS             5
-#define TABLE_DRIVER_SMU_CONFIG       6
-#define TABLE_ACTIVITY_MONITOR_COEFF  7
-#define TABLE_OVERDRIVE               8
-#define TABLE_I2C_COMMANDS            9
-#define TABLE_DRIVER_INFO             10
-#define TABLE_COUNT                   11
-
-#endif
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 12/67] drm/amd/display: Remove NULL assignment for stream_status
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (10 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 11/67] drm/amd/display: Remove dcn32_smu13 duplicate header Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 13/67] drm/amd/display: Change AVI Info Frame version to 4 for OVT Zaeem Mohamed
                   ` (54 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alvin Lee, Nicholas Choi, Zaeem Mohamed

From: Alvin Lee <alvin.lee2@amd.com>

[Description]
No need to assign stream_status NULL because it is always
re-assigned before usage. This change is to fix coverity
errors.

Reviewed-by: Nicholas Choi <nicholas.choi@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 873993a6513c..12687d400092 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -444,7 +444,6 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru
 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-			stream_status = NULL;
 			if (!pipe->stream)
 				continue;
 
@@ -464,7 +463,6 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru
 	for (i = 0, k = 0; context && i < dc->res_pool->pipe_count; i++) {
 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
 
-		stream_status = NULL;
 		if (!resource_is_pipe_type(pipe, OTG_MASTER))
 			continue;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 13/67] drm/amd/display: Change AVI Info Frame version to 4 for OVT
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (11 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 12/67] drm/amd/display: Remove NULL assignment for stream_status Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 14/67] drm/amd/display: Return after Init Zaeem Mohamed
                   ` (53 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Chris Park, Leo Ma, Zaeem Mohamed

From: Chris Park <chris.park@amd.com>

[Why]
Official Release CTA specification reverted the change and
no longer uses version 5 to indicate OVT timing.

[How]
Change the version used for AVI info Frame for OVT to 4.

Reviewed-by: Leo Ma <hanghong.ma@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 234236c43d21..61d6b5b21571 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -4287,7 +4287,7 @@ static void set_avi_info_frame(
 	}
 
 	if (rid != 0 && fr_ind != 0) {
-		hdmi_info.bits.header.version = 5;
+		hdmi_info.bits.header.version = 4;
 		hdmi_info.bits.header.length = 15;
 
 		hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 14/67] drm/amd/display: Return after Init
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (12 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 13/67] drm/amd/display: Change AVI Info Frame version to 4 for OVT Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 15/67] drm/amd/display: Fix multiple cursors when using 4 displays on a contiguous large surface Zaeem Mohamed
                   ` (52 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Daniel Sa, Dillon Varone, Zaeem Mohamed

From: Daniel Sa <daniel.sa@amd.com>

why:
DML21 being overwritten after init.

how:
After initializing, early return.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Daniel Sa <daniel.sa@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 17cc2fdd7d34..f5c2ab0c0d58 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -740,6 +740,7 @@ static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_op
 	// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.
         if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01 || in_dc->ctx->dce_version == DCN_VERSION_3_2)) {
                 dml21_reinit(in_dc, dml2, config);
+		return;
         }
 
 	// Store config options
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 15/67] drm/amd/display: Fix multiple cursors when using 4 displays on a contiguous large surface
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (13 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 14/67] drm/amd/display: Return after Init Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 16/67] drm/amd/display: reduce ODM slice count to initial new dc state only when needed Zaeem Mohamed
                   ` (51 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Nevenko Stupar, Alvin Lee, Zaeem Mohamed

From: Nevenko Stupar <nevenko.stupar@amd.com>

[Why & How]
Remove some cursor offset calculations for rotated cursor for fixing a bug where multiple cursors are seen.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nevenko Stupar <nevenko.stupar@amd.com>
---
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 25 -------------------
 1 file changed, 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 407a45a3ae2c..b9541d5ab601 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1126,10 +1126,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 	 */
 
 	if (param.rotation == ROTATION_ANGLE_90 || param.rotation == ROTATION_ANGLE_270) {
-		x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /
-			pipe_ctx->stream->src.height;
-		y_pos = pipe_ctx->stream->dst.y + y_pos * pipe_ctx->stream->dst.height /
-			pipe_ctx->stream->src.width;
 	} else {
 		x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /
 			pipe_ctx->stream->src.width;
@@ -1225,15 +1221,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 			}
 		}
 	} else if (param.rotation == ROTATION_ANGLE_90) {
-		if (!param.mirror) {
-			uint32_t temp_y = pos_cpy.y;
-
-			pos_cpy.y = pipe_ctx->plane_res.scl_data.recout.height - pos_cpy.x;
-			pos_cpy.x = temp_y - prev_odm_width;
-		} else {
-			swap(pos_cpy.x, pos_cpy.y);
-		}
-
 	} else if (param.rotation == ROTATION_ANGLE_270) {
 		// Swap axis and mirror vertically
 		uint32_t temp_x = pos_cpy.x;
@@ -1284,15 +1271,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 				pos_cpy.y = temp_x;
 			}
 		} else {
-			if (param.mirror) {
-				swap(pos_cpy.x, pos_cpy.y);
-
-				pos_cpy.x = pipe_ctx->plane_res.scl_data.recout.width - pos_cpy.x + 2 * pipe_ctx->plane_res.scl_data.recout.x;
-				pos_cpy.y = (2 * pipe_ctx->plane_res.scl_data.recout.y) + pipe_ctx->plane_res.scl_data.recout.height - pos_cpy.y;
-			} else {
-				pos_cpy.x = pipe_ctx->plane_res.scl_data.recout.width - pos_cpy.y;
-				pos_cpy.y = temp_x;
-			}
 		}
 	} else if (param.rotation == ROTATION_ANGLE_180) {
 		// Mirror horizontally and vertically
@@ -1320,7 +1298,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 					}
 				}
 			} else {
-				pos_cpy.x = recout_width - pos_cpy.x + 2 * recout_x;
 			}
 		}
 
@@ -1332,8 +1309,6 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 		 * Simplify it as:
 		 *   pos_cpy.y = recout.y * 2 + recout.height - pos_cpy.y
 		 */
-		pos_cpy.y = (2 * pipe_ctx->plane_res.scl_data.recout.y) +
-			pipe_ctx->plane_res.scl_data.recout.height - pos_cpy.y;
 	}
 
 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 16/67] drm/amd/display: reduce ODM slice count to initial new dc state only when needed
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (14 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 15/67] drm/amd/display: Fix multiple cursors when using 4 displays on a contiguous large surface Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 17/67] drm/amd/display: Update FIXED_VS retimer training pattern delay Zaeem Mohamed
                   ` (50 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu, Dillon Varone, Zaeem Mohamed

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
We need to decrease ODM slice when adding or removing planes because MPO
support takes precedence over dynamic ODM combine. However there is a case where
we remove ODM combine even for ODM combine required timing in the initial new
dc state. This is normally okay because ODM will be added back after we pass DML
bandwidth validation. However since we remove ODM combine in the initial new
state, the previous ODM pipe allocation is lost. This may cause the new plane to
take away the original secondary OPP head pipe that is still required in the new
state.

For a timing that requires ODM 2:1 but optimized with ODM 4:1, if we add an MPO
plane, we will not have enough pipe to preserve ODM 4:1. In this case we should
reduce ODM slice count then try to add the MPO plane again. By reducing, we are
gradually remove 1 ODM slice from right most side one at a time until we have
enough free pipes for the new plane. If we remove ODM combine entirely, we could
use the pipe at ODM slice index 1 as a DPP pipe for the new plane. But ODM slice
1 is still needed as the timing requires ODM 2:1. This transition is not
seamless and user will see corruption on the screen.

[how]
Remove single ODM slice one at time until we have enough pipes for a new plane.
Remove previous logic to always remove ODM combine entirely.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 45 +++++++------
 .../gpu/drm/amd/display/dc/core/dc_state.c    | 67 +++++++++++++------
 2 files changed, 71 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 61d6b5b21571..45a719fe884e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2596,6 +2596,17 @@ static void remove_hpo_dp_link_enc_from_ctx(struct resource_context *res_ctx,
 	}
 }
 
+static int get_num_of_free_pipes(const struct resource_pool *pool, const struct dc_state *context)
+{
+	int i;
+	int count = 0;
+
+	for (i = 0; i < pool->pipe_count; i++)
+		if (resource_is_pipe_type(&context->res_ctx.pipe_ctx[i], FREE_PIPE))
+			count++;
+	return count;
+}
+
 enum dc_status resource_add_otg_master_for_stream_output(struct dc_state *new_ctx,
 		const struct resource_pool *pool,
 		struct dc_stream_state *stream)
@@ -2729,37 +2740,33 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(
 		struct dc_state *cur_ctx,
 		struct resource_pool *pool)
 {
-	struct pipe_ctx *opp_head_pipe, *sec_pipe, *tail_pipe;
+	struct pipe_ctx *sec_pipe, *tail_pipe;
+	struct pipe_ctx *opp_heads[MAX_PIPES];
+	int opp_head_count;
+	int i;
 
 	if (!pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe) {
 		ASSERT(0);
 		return false;
 	}
 
-	opp_head_pipe = otg_master_pipe;
-	while (opp_head_pipe) {
+	opp_head_count = resource_get_opp_heads_for_otg_master(otg_master_pipe,
+			&new_ctx->res_ctx, opp_heads);
+	if (get_num_of_free_pipes(pool, new_ctx) < opp_head_count)
+		/* not enough free pipes */
+		return false;
+
+	for (i = 0; i < opp_head_count; i++) {
 		sec_pipe = pool->funcs->acquire_free_pipe_as_secondary_dpp_pipe(
 				cur_ctx,
 				new_ctx,
 				pool,
-				opp_head_pipe);
-		if (!sec_pipe) {
-			/* try tearing down MPCC combine */
-			int pipe_idx = acquire_first_split_pipe(
-					&new_ctx->res_ctx, pool,
-					otg_master_pipe->stream);
-
-			if (pipe_idx >= 0)
-				sec_pipe = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
-		}
-
-		if (!sec_pipe)
-			return false;
-
+				opp_heads[i]);
+		ASSERT(sec_pipe);
 		sec_pipe->plane_state = plane_state;
 
 		/* establish pipe relationship */
-		tail_pipe = get_tail_pipe(opp_head_pipe);
+		tail_pipe = get_tail_pipe(opp_heads[i]);
 		tail_pipe->bottom_pipe = sec_pipe;
 		sec_pipe->top_pipe = tail_pipe;
 		sec_pipe->bottom_pipe = NULL;
@@ -2770,8 +2777,6 @@ static bool acquire_secondary_dpp_pipes_and_add_plane(
 		} else {
 			sec_pipe->prev_odm_pipe = NULL;
 		}
-
-		opp_head_pipe = opp_head_pipe->next_odm_pipe;
 	}
 	return true;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
index 06b22897137e..c75dcdc20428 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c
@@ -442,6 +442,19 @@ enum dc_status dc_state_remove_stream(
 	return DC_OK;
 }
 
+static void remove_mpc_combine_for_stream(const struct dc *dc,
+		struct dc_state *new_ctx,
+		const struct dc_state *cur_ctx,
+		struct dc_stream_status *status)
+{
+	int i;
+
+	for (i = 0; i < status->plane_count; i++)
+		resource_update_pipes_for_plane_with_slice_count(
+				new_ctx, cur_ctx, dc->res_pool,
+				status->plane_states[i], 1);
+}
+
 bool dc_state_add_plane(
 		const struct dc *dc,
 		struct dc_stream_state *stream,
@@ -452,8 +465,12 @@ bool dc_state_add_plane(
 	struct pipe_ctx *otg_master_pipe;
 	struct dc_stream_status *stream_status = NULL;
 	bool added = false;
+	int odm_slice_count;
+	int i;
 
 	stream_status = dc_state_get_stream_status(state, stream);
+	otg_master_pipe = resource_get_otg_master_for_stream(
+			&state->res_ctx, stream);
 	if (stream_status == NULL) {
 		dm_error("Existing stream not found; failed to attach surface!\n");
 		goto out;
@@ -461,22 +478,39 @@ bool dc_state_add_plane(
 		dm_error("Surface: can not attach plane_state %p! Maximum is: %d\n",
 				plane_state, MAX_SURFACE_NUM);
 		goto out;
+	} else if (!otg_master_pipe) {
+		goto out;
 	}
 
-	if (stream_status->plane_count == 0 && dc->config.enable_windowed_mpo_odm)
-		/* ODM combine could prevent us from supporting more planes
-		 * we will reset ODM slice count back to 1 when all planes have
-		 * been removed to maximize the amount of planes supported when
-		 * new planes are added.
-		 */
-		resource_update_pipes_for_stream_with_slice_count(
-				state, dc->current_state, dc->res_pool, stream, 1);
+	added = resource_append_dpp_pipes_for_plane_composition(state,
+			dc->current_state, pool, otg_master_pipe, plane_state);
 
-	otg_master_pipe = resource_get_otg_master_for_stream(
-			&state->res_ctx, stream);
-	if (otg_master_pipe)
+	if (!added) {
+		/* try to remove MPC combine to free up pipes */
+		for (i = 0; i < state->stream_count; i++)
+			remove_mpc_combine_for_stream(dc, state,
+					dc->current_state,
+					&state->stream_status[i]);
 		added = resource_append_dpp_pipes_for_plane_composition(state,
-				dc->current_state, pool, otg_master_pipe, plane_state);
+					dc->current_state, pool,
+					otg_master_pipe, plane_state);
+	}
+
+	if (!added) {
+		/* try to decrease ODM slice count gradually to free up pipes */
+		odm_slice_count = resource_get_odm_slice_count(otg_master_pipe);
+		for (i = odm_slice_count - 1; i > 0; i--) {
+			resource_update_pipes_for_stream_with_slice_count(state,
+					dc->current_state, dc->res_pool, stream,
+					i);
+			added = resource_append_dpp_pipes_for_plane_composition(
+					state,
+					dc->current_state, pool,
+					otg_master_pipe, plane_state);
+			if (added)
+				break;
+		}
+	}
 
 	if (added) {
 		stream_status->plane_states[stream_status->plane_count] =
@@ -536,15 +570,6 @@ bool dc_state_remove_plane(
 
 	stream_status->plane_states[stream_status->plane_count] = NULL;
 
-	if (stream_status->plane_count == 0 && dc->config.enable_windowed_mpo_odm)
-		/* ODM combine could prevent us from supporting more planes
-		 * we will reset ODM slice count back to 1 when all planes have
-		 * been removed to maximize the amount of planes supported when
-		 * new planes are added.
-		 */
-		resource_update_pipes_for_stream_with_slice_count(
-				state, dc->current_state, dc->res_pool, stream, 1);
-
 	return true;
 }
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 17/67] drm/amd/display: Update FIXED_VS retimer training pattern delay
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (15 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 16/67] drm/amd/display: reduce ODM slice count to initial new dc state only when needed Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 18/67] drm/amd/display: Add fallback defaults for invalid LTTPR DPCD caps Zaeem Mohamed
                   ` (49 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Michael Strauss, Wenjing Liu, Zaeem Mohamed

From: Michael Strauss <michael.strauss@amd.com>

[WHY]
Needed for PHY patterns as well to perform electrical compliance.
Also need to increase wait time from 30ms to 50ms to resolve very
intermittent UHBR20 link training failures.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
 .../dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c     | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
index 5302d2c9c760..116ff37126e7 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_fixed_vs_pe_retimer_dp.c
@@ -168,9 +168,9 @@ static void set_hpo_fixed_vs_pe_retimer_dp_link_test_pattern(struct dc_link *lin
 
 	link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
 
-	// Give retimer extra time to lock before updating DP_TRAINING_PATTERN_SET to TPS1
-	if (tp_params->dp_phy_pattern == DP_TEST_PATTERN_128b_132b_TPS1_TRAINING_MODE)
-		msleep(30);
+	// Give retimer extra time to lock before updating DP_TRAINING_PATTERN_SET to TPS1 or phy pattern
+	if (tp_params->dp_phy_pattern != DP_TEST_PATTERN_128b_132b_TPS2_TRAINING_MODE)
+		msleep(50);
 }
 
 static void set_hpo_fixed_vs_pe_retimer_dp_lane_settings(struct dc_link *link,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 18/67] drm/amd/display: Add fallback defaults for invalid LTTPR DPCD caps
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (16 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 17/67] drm/amd/display: Update FIXED_VS retimer training pattern delay Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 19/67] drm/amd/display: Ignore phantom DTBCLK requirement Zaeem Mohamed
                   ` (48 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Michael Strauss, George Shen, Wenjing Liu,
	Zaeem Mohamed

From: Michael Strauss <michael.strauss@amd.com>

[WHY]
Some sinks are observed to return invalid LTTPR revision and/or invalid
LTTPR link rate capabilities.

[HOW]
Assume any LTTPR which reports invalid max link rate supports HBR3.
Don't validate LTTPR DPCD revision in dp_is_lttpr_present check.

Reviewed-by: George Shen <george.shen@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
---
 .../dc/link/protocols/link_dp_capability.c    | 19 ++++++++++++++++---
 1 file changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 964abccebdc6..1ff9876e3ca3 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -363,10 +363,10 @@ bool dp_is_128b_132b_signal(struct pipe_ctx *pipe_ctx)
 
 bool dp_is_lttpr_present(struct dc_link *link)
 {
+	/* Some sink devices report invalid LTTPR revision, so don't validate against that cap */
 	return (dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt) != 0 &&
 			link->dpcd_caps.lttpr_caps.max_lane_count > 0 &&
-			link->dpcd_caps.lttpr_caps.max_lane_count <= 4 &&
-			link->dpcd_caps.lttpr_caps.revision.raw >= 0x14);
+			link->dpcd_caps.lttpr_caps.max_lane_count <= 4);
 }
 
 /* in DP compliance test, DPR-120 may have
@@ -399,7 +399,20 @@ static enum dc_link_rate get_link_rate_from_max_link_bw(
 
 static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link)
 {
-	enum dc_link_rate lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
+
+	enum dc_link_rate lttpr_max_link_rate = LINK_RATE_UNKNOWN;
+
+	switch (link->dpcd_caps.lttpr_caps.max_link_rate) {
+	case LINK_RATE_LOW:
+	case LINK_RATE_HIGH:
+	case LINK_RATE_HIGH2:
+	case LINK_RATE_HIGH3:
+		lttpr_max_link_rate = link->dpcd_caps.lttpr_caps.max_link_rate;
+		break;
+	default:
+		// Assume all LTTPRs support up to HBR3 to improve misbehaving sink interop
+		lttpr_max_link_rate = LINK_RATE_HIGH3;
+	}
 
 	if (link->dpcd_caps.lttpr_caps.supported_128b_132b_rates.bits.UHBR20)
 		lttpr_max_link_rate = LINK_RATE_UHBR20;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 19/67] drm/amd/display: Ignore phantom DTBCLK requirement
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (17 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 18/67] drm/amd/display: Add fallback defaults for invalid LTTPR DPCD caps Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 20/67] drm/amd/display: Add sequential ONO sequencing for DCN35 Zaeem Mohamed
                   ` (47 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alvin Lee, Dillon Varone, Zaeem Mohamed

From: Alvin Lee <alvin.lee2@amd.com>

[Description]
Phantom DTBCLK can be calculated different from main because phantom
has no DSC and thus will have a different output BPP. Ignore phantom
DTBCLK requirement and only consider non-phantom DTBCLK requirements.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
 .../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index 85eee5ab5443..2b240a30d2ec 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -7713,7 +7713,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out
 
 	mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = false;
 	for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
-		if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl) {
+		if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_encoder == dml2_hdmifrl &&
+				!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k])) {
 			mode_lib->ms.RequiredDTBCLK[k] = RequiredDTBCLK(
 				mode_lib->ms.RequiresDSC[k],
 				s->PixelClockBackEnd[k],
@@ -7728,6 +7729,13 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out
 			if (mode_lib->ms.RequiredDTBCLK[k] > ((double)min_clk_table->max_clocks_khz.dtbclk / 1000)) {
 				mode_lib->ms.support.DTBCLKRequiredMoreThanSupported = true;
 			}
+		} else {
+			/* Phantom DTBCLK can be calculated different from main because phantom has no DSC and thus
+			 * will have a different output BPP. Ignore phantom DTBCLK requirement and only consider
+			 * non-phantom DTBCLK requirements. In map_mode_to_soc_dpm we choose the highest DTBCLK
+			 * required - by setting phantom dtbclk to 0 we ignore it.
+			 */
+			mode_lib->ms.RequiredDTBCLK[k] = 0;
 		}
 	}
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 20/67] drm/amd/display: Add sequential ONO sequencing for DCN35
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (18 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 19/67] drm/amd/display: Ignore phantom DTBCLK requirement Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 21/67] drm/amd/display: [FW Promotion] Release 0.0.220.0 Zaeem Mohamed
                   ` (46 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Nicholas Kazlauskas, Sung joon Kim, Zaeem Mohamed

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
Adds support for performing the sequential ONO changes from DCN351
into DCN35 ASIC based on revision.

[How]
Check the revision and run the DCN351 sequences on applicable revisions.

Reviewed-by: Sung joon Kim <sungjoon.kim@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h           |  1 +
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 85 +++++++++++++++----
 .../dc/resource/dcn35/dcn35_resource.c        |  4 +
 3 files changed, 75 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c78296b06b79..1008cab97c76 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -291,6 +291,7 @@ struct dc_caps {
 	uint8_t subvp_drr_vblank_start_margin_us;
 	bool cursor_not_scaled;
 	bool dcmode_power_limits_present;
+	bool sequential_ono;
 };
 
 struct dc_bug_wa {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 2b3ba5971c69..4f87316e1318 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -1078,6 +1078,19 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context,
 		update_state->pg_pipe_res_update[PG_OPTC][0] = false;
 	}
 
+	if (dc->caps.sequential_ono) {
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (!update_state->pg_pipe_res_update[PG_HUBP][i] &&
+			    !update_state->pg_pipe_res_update[PG_DPP][i]) {
+				for (j = i - 1; j >= 0; j--) {
+					update_state->pg_pipe_res_update[PG_HUBP][j] = false;
+					update_state->pg_pipe_res_update[PG_DPP][j] = false;
+				}
+
+				break;
+			}
+		}
+	}
 }
 
 void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
@@ -1177,6 +1190,19 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
 	if (hpo_frl_stream_enc_acquired)
 		update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true;
 
+	if (dc->caps.sequential_ono) {
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
+			    update_state->pg_pipe_res_update[PG_DPP][i]) {
+				for (j = i - 1; j >= 0; j--) {
+					update_state->pg_pipe_res_update[PG_HUBP][j] = true;
+					update_state->pg_pipe_res_update[PG_DPP][j] = true;
+				}
+
+				break;
+			}
+		}
+	}
 }
 
 /**
@@ -1197,6 +1223,8 @@ void dcn35_calc_blocks_to_ungate(struct dc *dc, struct dc_state *context,
  *	ONO Region 2, DCPG 24: mpc opp optc dwb
  *	ONO Region 0, DCPG 22: dccg dio dcio - SKIPPED. will be pwr dwn after lono timer is armed
  *
+ * If sequential ONO is specified the order is modified from ONO Region 11 -> ONO Region 0 descending.
+ *
  * @dc: Current DC state
  * @update_state: update PG sequence states for HW block
  */
@@ -1216,19 +1244,35 @@ void dcn35_hw_block_power_down(struct dc *dc,
 			pg_cntl->funcs->hpo_pg_control(pg_cntl, false);
 	}
 
-	for (i = 0; i < dc->res_pool->pipe_count; i++) {
-		if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
-			update_state->pg_pipe_res_update[PG_DPP][i]) {
-			if (pg_cntl->funcs->hubp_dpp_pg_control)
-				pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
+	if (!dc->caps.sequential_ono) {
+		for (i = 0; i < dc->res_pool->pipe_count; i++) {
+			if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
+			    update_state->pg_pipe_res_update[PG_DPP][i]) {
+				if (pg_cntl->funcs->hubp_dpp_pg_control)
+					pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
+			}
 		}
-	}
-	for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++)
-		if (update_state->pg_pipe_res_update[PG_DSC][i]) {
-			if (pg_cntl->funcs->dsc_pg_control)
-				pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
+
+		for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
+			if (update_state->pg_pipe_res_update[PG_DSC][i]) {
+				if (pg_cntl->funcs->dsc_pg_control)
+					pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
+			}
 		}
+	} else {
+		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
+			if (update_state->pg_pipe_res_update[PG_DSC][i]) {
+				if (pg_cntl->funcs->dsc_pg_control)
+					pg_cntl->funcs->dsc_pg_control(pg_cntl, i, false);
+			}
 
+			if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
+			    update_state->pg_pipe_res_update[PG_DPP][i]) {
+				if (pg_cntl->funcs->hubp_dpp_pg_control)
+					pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, false);
+			}
+		}
+	}
 
 	/*this will need all the clients to unregister optc interruts let dmubfw handle this*/
 	if (pg_cntl->funcs->plane_otg_pg_control)
@@ -1256,6 +1300,8 @@ void dcn35_hw_block_power_down(struct dc *dc,
  *	ONO Region 10, DCPG 3: dchubp3, dpp3
  *	ONO Region 3, DCPG 25: hpo - SKIPPED
  *
+ * If sequential ONO is specified the order is modified from ONO Region 0 -> ONO Region 11 ascending.
+ *
  * @dc: Current DC state
  * @update_state: update PG sequence states for HW block
  */
@@ -1274,11 +1320,13 @@ void dcn35_hw_block_power_up(struct dc *dc,
 	if (pg_cntl->funcs->plane_otg_pg_control)
 		pg_cntl->funcs->plane_otg_pg_control(pg_cntl, true);
 
-	for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++)
-		if (update_state->pg_pipe_res_update[PG_DSC][i]) {
-			if (pg_cntl->funcs->dsc_pg_control)
-				pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
-		}
+	if (!dc->caps.sequential_ono) {
+		for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++)
+			if (update_state->pg_pipe_res_update[PG_DSC][i]) {
+				if (pg_cntl->funcs->dsc_pg_control)
+					pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
+			}
+	}
 
 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
 		if (update_state->pg_pipe_res_update[PG_HUBP][i] &&
@@ -1286,6 +1334,13 @@ void dcn35_hw_block_power_up(struct dc *dc,
 			if (pg_cntl->funcs->hubp_dpp_pg_control)
 				pg_cntl->funcs->hubp_dpp_pg_control(pg_cntl, i, true);
 		}
+
+		if (dc->caps.sequential_ono) {
+			if (update_state->pg_pipe_res_update[PG_DSC][i]) {
+				if (pg_cntl->funcs->dsc_pg_control)
+					pg_cntl->funcs->dsc_pg_control(pg_cntl, i, true);
+			}
+		}
 	}
 	if (update_state->pg_res_update[PG_HPO]) {
 		if (pg_cntl->funcs->hpo_pg_control)
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 28c459907698..391f9f69a923 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1891,6 +1891,10 @@ static bool dcn35_resource_construct(
 	 */
 	dc->caps.max_disp_clock_khz_at_vmin = 650000;
 
+	/* Sequential ONO is based on ASIC. */
+	if (dc->ctx->asic_id.hw_internal_rev > 0x10)
+		dc->caps.sequential_ono = true;
+
 	/* Use pipe context based otg sync logic */
 	dc->config.use_pipe_ctx_sync_logic = true;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 21/67] drm/amd/display: [FW Promotion] Release 0.0.220.0
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (19 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 20/67] drm/amd/display: Add sequential ONO sequencing for DCN35 Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 22/67] drm/amd/display: added NULL check at start of dc_validate_stream Zaeem Mohamed
                   ` (45 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Anthony Koo, Zaeem Mohamed

From: Anthony Koo <anthony.koo@amd.com>

 - Change ordering of structs to put enums together
 - Add new define DMUB_TRACE_ENTRY_DEFINED to guard
   the trace code enum

Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 26 ++++++++++---------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index fe529b67369e..7fea9bec7b64 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -558,6 +558,7 @@ union dmub_fw_meta {
 //==============================================================================
 //< DMUB Trace Buffer>================================================================
 //==============================================================================
+#if !defined(TENSILICA) && !defined(DMUB_TRACE_ENTRY_DEFINED)
 /**
  * dmub_trace_code_t - firmware trace code, 32-bits
  */
@@ -572,6 +573,7 @@ struct dmcub_trace_buf_entry {
 	uint32_t param0; /**< trace defined parameter 0 */
 	uint32_t param1; /**< trace defined parameter 1 */
 };
+#endif
 
 //==============================================================================
 //< DMUB_STATUS>================================================================
@@ -2538,6 +2540,18 @@ enum dmub_cmd_psr_type {
 	DMUB_CMD__SET_PSR_POWER_OPT = 7,
 };
 
+/**
+ * Different PSR residency modes.
+ * Different modes change the definition of PSR residency.
+ */
+enum psr_residency_mode {
+	PSR_RESIDENCY_MODE_PHY = 0,
+	PSR_RESIDENCY_MODE_ALPM,
+	PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
+	/* Do not add below. */
+	PSR_RESIDENCY_MODE_LAST_ELEMENT,
+};
+
 enum dmub_cmd_fams_type {
 	DMUB_CMD__FAMS_SETUP_FW_CTRL	= 0,
 	DMUB_CMD__FAMS_DRR_UPDATE		= 1,
@@ -3259,18 +3273,6 @@ struct dmub_rb_cmd_psr_set_power_opt {
 	struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
 };
 
-/**
- * Different PSR residency modes.
- * Different modes change the definition of PSR residency.
- */
-enum psr_residency_mode {
-	PSR_RESIDENCY_MODE_PHY = 0,
-	PSR_RESIDENCY_MODE_ALPM,
-	PSR_RESIDENCY_MODE_ENABLEMENT_PERIOD,
-	/* Do not add below. */
-	PSR_RESIDENCY_MODE_LAST_ELEMENT,
-};
-
 /**
  * Definition of Replay Residency GPINT command.
  * Bit[0] - Residency mode for Revision 0
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 22/67] drm/amd/display: added NULL check at start of dc_validate_stream
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (20 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 21/67] drm/amd/display: [FW Promotion] Release 0.0.220.0 Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 23/67] drm/amd/display: Add config support entry to replay caps debugfs Zaeem Mohamed
                   ` (44 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, winstang, Alvin Lee, Zaeem Mohamed

From: winstang <winstang@amd.com>

[Why]
prevent invalid memory access

[How]
check if dc and stream are NULL

Co-authored-by: winstang <winstang@amd.com>
Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: winstang <winstang@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 45a719fe884e..6d4d4c95243f 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -4754,6 +4754,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
 
 enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
 {
+	if (dc == NULL || stream == NULL)
+		return DC_ERROR_UNEXPECTED;
+
 	struct dc_link *link = stream->link;
 	struct timing_generator *tg = dc->res_pool->timing_generators[0];
 	enum dc_status res = DC_OK;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 23/67] drm/amd/display: Add config support entry to replay caps debugfs
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (21 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 22/67] drm/amd/display: added NULL check at start of dc_validate_stream Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 24/67] drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max link rate Zaeem Mohamed
                   ` (43 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

From: Roman Li <roman.li@amd.com>

[Why]
replay_capability debugfs tells whether sink and driver support
replay feature. However replay enablement also depends on
whether it is enabled/disabled via amdgpu module params.

[How]
Add 'Config support' entry to output current replay config.

Reviewed-by: ChiaHsuan Chung <user did not set an email>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 8db75afa9fc9..7cfa240a3cea 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -1008,6 +1008,7 @@ static int replay_capability_show(struct seq_file *m, void *data)
 
 	seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay));
 	seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay));
+	seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported));
 
 	return 0;
 }
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 24/67] drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max link rate
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (22 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 23/67] drm/amd/display: Add config support entry to replay caps debugfs Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 25/67] drm/amd/display: Remove duplicate 'update_idle_uclk' in dcn401 clk_mgr code Zaeem Mohamed
                   ` (42 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, George Shen, Wenjing Liu, Zaeem Mohamed

From: George Shen <george.shen@amd.com>

[Why]
Passive DP40 cables were updated in the latest DP spec to support
UHBR13.5 link rate. Current max link rate logic checks against the
cable ID DPCD even for passive cables.

[How]
Ignore UHBR13.5 cable ID DPCD cap in get_max_link_rate logic.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
---
 .../gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 1ff9876e3ca3..41bdadc585b3 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -2124,7 +2124,8 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link)
 		if (cable_max_link_rate < max_link_cap.link_rate)
 			max_link_cap.link_rate = cable_max_link_rate;
 
-		if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY)
+		if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY &&
+				link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2)
 			is_uhbr13_5_supported = false;
 	}
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 25/67] drm/amd/display: Remove duplicate 'update_idle_uclk' in dcn401 clk_mgr code
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (23 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 24/67] drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max link rate Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 26/67] drm/amd/display: Use the SPDX license identifier for dmub_replay files Zaeem Mohamed
                   ` (41 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Ivan Lipski, Alex Hung, Zaeem Mohamed

From: Ivan Lipski <ivlipski@amd.com>

[WHY]
The coverity analysis flagged this if expression as it contains a
'CONSTANT_EXPRESSION_RESULT': 'update_idle_uclk' is 'ORd' with itself.

[HOW]
Remove the duplicate 'update_idle_uclk'.

Reviewed-by: Alex Hung <alex.hung@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Ivan Lipski <ivlipski@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 0fbe615069f0..28769deaad37 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -940,7 +940,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 	}
 
 	/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
-	if ((update_idle_uclk || update_idle_uclk) && is_idle_dpm_enabled) {
+	if (update_idle_uclk && is_idle_dpm_enabled) {
 		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
 		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 26/67] drm/amd/display: Use the SPDX license identifier for dmub_replay files
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (24 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 25/67] drm/amd/display: Remove duplicate 'update_idle_uclk' in dcn401 clk_mgr code Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 27/67] drm/amd/display: DCN401 cusor code update Zaeem Mohamed
                   ` (40 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Rodrigo Siqueira, Aurabindo Pillai, Zaeem Mohamed

From: Rodrigo Siqueira <rodrigo.siqueira@amd.com>

Use the SPDX format for dmub_replay.c|.h files.

Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dmub_replay.c  | 27 ++---------------
 .../gpu/drm/amd/display/dc/dce/dmub_replay.h  | 29 +++----------------
 2 files changed, 7 insertions(+), 49 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 62e03fdf813b..5437ebd8bc21 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -1,27 +1,6 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2024 Advanced Micro Devices, Inc.
 
 #include "dc.h"
 #include "dc_dmub_srv.h"
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
index 63bbb1bb0ad5..9b20df9258bd 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
@@ -1,28 +1,7 @@
-/*
- * Copyright 2023 Advanced Micro Devices, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: AMD
- *
- */
-
+// SPDX-License-Identifier: MIT
+//
+// Copyright 2024 Advanced Micro Devices, Inc.
+ 
 #ifndef _DMUB_REPLAY_H_
 #define _DMUB_REPLAY_H_
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 27/67] drm/amd/display: DCN401 cusor code update
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (25 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 26/67] drm/amd/display: Use the SPDX license identifier for dmub_replay files Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 28/67] drm/amd/display: Prevent overflow on DTO calculation Zaeem Mohamed
                   ` (39 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Sridevi Arvindekar, Ariel Bernstein, Nevenko Stupar,
	Zaeem Mohamed

From: Sridevi Arvindekar <sarvinde@amd.com>

Scaling androtation changes for cursor.

Reviewed-by: Ariel Bernstein <eric.bernstein@amd.com>
Reviewed-by: Nevenko Stupar <nevenko.stupar@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Sridevi Arvindekar <sarvinde@amd.com>
---
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 22 +++++--------------
 1 file changed, 5 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index b9541d5ab601..0b00fdf1297a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1124,14 +1124,10 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 	 * pipe to make sure each pipe enabling cursor on its part of the
 	 * screen.
 	 */
-
-	if (param.rotation == ROTATION_ANGLE_90 || param.rotation == ROTATION_ANGLE_270) {
-	} else {
-		x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /
-			pipe_ctx->stream->src.width;
-		y_pos = pipe_ctx->stream->dst.y + y_pos * pipe_ctx->stream->dst.height /
-			pipe_ctx->stream->src.height;
-	}
+	x_pos = pipe_ctx->stream->dst.x + x_pos * pipe_ctx->stream->dst.width /
+		pipe_ctx->stream->src.width;
+	y_pos = pipe_ctx->stream->dst.y + y_pos * pipe_ctx->stream->dst.height /
+		pipe_ctx->stream->src.height;
 
 	/**
 	 * If the cursor's source viewport is clipped then we need to
@@ -1297,18 +1293,10 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 						pos_cpy.x = temp_x + recout_width;
 					}
 				}
-			} else {
 			}
+
 		}
 
-		/**
-		 * Display groups that are 1xnY, have pos_cpy.y > recout.height
-		 * Calculation:
-		 *   delta_from_bottom = recout.y + recout.height - pos_cpy.y
-		 *   pos_cpy.y_new = recout.y + delta_from_bottom
-		 * Simplify it as:
-		 *   pos_cpy.y = recout.y * 2 + recout.height - pos_cpy.y
-		 */
 	}
 
 	hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 28/67] drm/amd/display: Prevent overflow on DTO calculation
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (26 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 27/67] drm/amd/display: DCN401 cusor code update Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 29/67] drm/amd/display: Disable boot optimization for DCN401 Zaeem Mohamed
                   ` (38 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Chris Park, Alvin Lee, Zaeem Mohamed

From: Chris Park <chris.park@amd.com>

[Why]
uint32_t is implicitly converted to uint64_t while multiplication
still happens on uint32_t side.  This creates digit overflow
for large pixel clock which is meant to be retained in uint64_t.

[How]
Calculate multiplication of units in uint64_t domain instead of
uint32_t in DTO parameter clock caculation.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
---
 .../gpu/drm/amd/display/dc/dce/dce_clock_source.c    | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 63deb5b60548..042a4187fff4 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -1088,11 +1088,15 @@ static bool dcn401_program_pix_clk(
 		dto_params.clk_src = DPREFCLK;
 
 		if (e) {
-			dto_params.pixclk_hz = e->target_pixel_rate_khz * e->mult_factor;
-			dto_params.refclk_hz = dtbclk_p_src_clk_khz * e->div_factor;
+			dto_params.pixclk_hz = e->target_pixel_rate_khz;
+			dto_params.pixclk_hz *= e->mult_factor;
+			dto_params.refclk_hz = dtbclk_p_src_clk_khz;
+			dto_params.refclk_hz *= e->div_factor;
 		} else {
-			dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz * 100;
-			dto_params.refclk_hz = dtbclk_p_src_clk_khz * 1000;
+			dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz;
+			dto_params.pixclk_hz *= 100;
+			dto_params.refclk_hz = dtbclk_p_src_clk_khz;
+			dto_params.refclk_hz *= 1000;
 		}
 
 		/* enable DP DTO */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 29/67] drm/amd/display: Disable boot optimization for DCN401
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (27 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 28/67] drm/amd/display: Prevent overflow on DTO calculation Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 30/67] drm/amd/display: Update efficiency bandwidth for dcn351 Zaeem Mohamed
                   ` (37 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Joshua Aberback, Alvin Lee, Zaeem Mohamed

From: Joshua Aberback <joshua.aberback@amd.com>

[Why]
DCN401 currently has an issue re-enabling when pipe splitting is enabled,
while the root cause is being investigated we can make sure everything is
being reset as a workaround, by disabling boot optimization.

[How]
 - use enable_accelerated_mode instead of init_pipes to fully reset asic

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
---
 .../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c    | 9 ++++++++-
 .../drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 +
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 0b00fdf1297a..776ec8963cab 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -304,7 +304,14 @@ void dcn401_init_hw(struct dc *dc)
 	 * everything down.
 	 */
 	if (dcb->funcs->is_accelerated_mode(dcb) || !dc->config.seamless_boot_edp_requested) {
-		hws->funcs.init_pipes(dc, dc->current_state);
+		/* Disable boot optimizations means power down everything including PHY, DIG,
+		 * and OTG (i.e. the boot is not optimized because we do a full power down).
+		 */
+		if (dc->hwss.enable_accelerated_mode && dc->debug.disable_boot_optimizations)
+			dc->hwss.enable_accelerated_mode(dc, dc->current_state);
+		else
+			hws->funcs.init_pipes(dc, dc->current_state);
+
 		if (dc->res_pool->hubbub->funcs->allow_self_refresh_control)
 			dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub,
 					!dc->res_pool->hubbub->ctx->dc->debug.disable_stutter);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index 7781a0342d67..ea803df8645e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -733,6 +733,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.force_cositing = CHROMA_COSITING_TOPLEFT + 1,
 	.disable_idle_power_optimizations = true,
 	.edp_oled_no_backlight_enable = true,
+	.disable_boot_optimizations = true,
 };
 
 static struct dce_aux *dcn401_aux_engine_create(
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 30/67] drm/amd/display: Update efficiency bandwidth for dcn351
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (28 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 29/67] drm/amd/display: Disable boot optimization for DCN401 Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 31/67] drm/amd/display: Avoid programming DTO if Refclk is 0 Zaeem Mohamed
                   ` (36 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Harry Wentland, Zaeem Mohamed

From: Fangzhi Zuo <jerry.zuo@amd.com>

Fixing 4k240 underflow on dcn351

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
index 935893456849..8b9dcee77266 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c
@@ -296,6 +296,7 @@ void dml2_init_socbb_params(struct dml2_context *dml2, const struct dc *in_dc, s
 		out->round_trip_ping_latency_dcfclk_cycles = 106;
 		out->smn_latency_us = 2;
 		out->dispclk_dppclk_vco_speed_mhz = 3600;
+		out->pct_ideal_dram_bw_after_urgent_pixel_only = 65.0;
 		break;
 
 	case dml_project_dcn401:
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 31/67] drm/amd/display: Avoid programming DTO if Refclk is 0
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (29 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 30/67] drm/amd/display: Update efficiency bandwidth for dcn351 Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 32/67] drm/amd/display: Adjust debug msg for usb4/tbt Zaeem Mohamed
                   ` (35 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Chris Park, Dillon Varone, Zaeem Mohamed

From: Chris Park <chris.park@amd.com>

[Why]
Reference clock, either DPREFCLK or DTBCLK can be a value of 0
which then will encounter division by 0.

[How]
Avoid further calculation and programming if refclk is not
populated.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Chris Park <chris.park@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index 3538e190f217..dac31c4cf2a7 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -603,6 +603,10 @@ static void dccg401_set_dp_dto(
 		BREAK_TO_DEBUGGER();
 		return;
 	}
+	if (!params->refclk_hz) {
+		BREAK_TO_DEBUGGER();
+		return;
+	}
 
 	if (!dc_is_tmds_signal(params->signal)) {
 		uint64_t dto_integer;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 32/67] drm/amd/display: Adjust debug msg for usb4/tbt
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (30 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 31/67] drm/amd/display: Avoid programming DTO if Refclk is 0 Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 33/67] drm/amd/display: Defer the setting of link hpd status " Zaeem Mohamed
                   ` (34 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

From: Wayne Lin <wayne.lin@amd.com>

[Why & How]
Debug msg for usb4/tbt now is a bit confusing. Adjust it for better reading.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 57 +++++++++++--------
 1 file changed, 34 insertions(+), 23 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 27acbe3ff57b..52fbd5ec7f8d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -774,9 +774,9 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,
 		aconnector = to_amdgpu_dm_connector(connector);
 		if (link && aconnector->dc_link == link) {
 			if (notify->type == DMUB_NOTIFICATION_HPD)
-				DRM_INFO("DMUB HPD callback: link_index=%u\n", link_index);
-			else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
 				DRM_INFO("DMUB HPD IRQ callback: link_index=%u\n", link_index);
+			else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
+				DRM_INFO("DMUB HPD RX IRQ callback: link_index=%u\n", link_index);
 			else
 				DRM_WARN("DMUB Unknown HPD callback type %d, link_index=%u\n",
 						notify->type, link_index);
@@ -788,10 +788,13 @@ static void dmub_hpd_callback(struct amdgpu_device *adev,
 	drm_connector_list_iter_end(&iter);
 
 	if (hpd_aconnector) {
-		if (notify->type == DMUB_NOTIFICATION_HPD)
+		if (notify->type == DMUB_NOTIFICATION_HPD) {
+			if (hpd_aconnector->dc_link->hpd_status == (notify->hpd_status == DP_HPD_PLUG))
+				DRM_WARN("DMUB reported hpd status unchanged. link_index=%u\n", link_index);
 			handle_hpd_irq_helper(hpd_aconnector);
-		else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ)
+		} else if (notify->type == DMUB_NOTIFICATION_HPD_IRQ) {
 			handle_hpd_rx_irq(hpd_aconnector);
+		}
 	}
 }
 
@@ -860,6 +863,31 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 	u32 count = 0;
 	struct dmub_hpd_work *dmub_hpd_wrk;
 	struct dc_link *plink = NULL;
+	static const char *const event_type[] = {
+		"NO_DATA",
+		"AUX_REPLY",
+		"HPD",
+		"HPD_IRQ",
+		"SET_CONFIGC_REPLY",
+		"DPIA_NOTIFICATION",
+	};
+
+	do {
+		if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
+			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
+							entry.param0, entry.param1);
+
+			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
+				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
+		} else
+			break;
+
+		count++;
+
+	} while (count <= DMUB_TRACE_MAX_READ);
+
+	if (count > DMUB_TRACE_MAX_READ)
+		DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 
 	if (dc_enable_dmub_notifications(adev->dm.dc) &&
 		irq_params->irq_src == DC_IRQ_SOURCE_DMCUB_OUTBOX) {
@@ -871,7 +899,8 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 				continue;
 			}
 			if (!dm->dmub_callback[notify.type]) {
-				DRM_DEBUG_DRIVER("DMUB notification skipped, no handler: type=%d\n", notify.type);
+				DRM_WARN("DMUB notification skipped due to no handler: type=%s\n",
+					event_type[notify.type]);
 				continue;
 			}
 			if (dm->dmub_thread_offload[notify.type] == true) {
@@ -902,24 +931,6 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 			}
 		} while (notify.pending_notification);
 	}
-
-
-	do {
-		if (dc_dmub_srv_get_dmub_outbox0_msg(dm->dc, &entry)) {
-			trace_amdgpu_dmub_trace_high_irq(entry.trace_code, entry.tick_count,
-							entry.param0, entry.param1);
-
-			DRM_DEBUG_DRIVER("trace_code:%u, tick_count:%u, param0:%u, param1:%u\n",
-				 entry.trace_code, entry.tick_count, entry.param0, entry.param1);
-		} else
-			break;
-
-		count++;
-
-	} while (count <= DMUB_TRACE_MAX_READ);
-
-	if (count > DMUB_TRACE_MAX_READ)
-		DRM_DEBUG_DRIVER("Warning : count > DMUB_TRACE_MAX_READ");
 }
 
 static int dm_set_clockgating_state(void *handle,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 33/67] drm/amd/display: Defer the setting of link hpd status for usb4/tbt
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (31 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 32/67] drm/amd/display: Adjust debug msg for usb4/tbt Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:55 ` [PATCH 34/67] drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAX Zaeem Mohamed
                   ` (33 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

From: Wayne Lin <wayne.lin@amd.com>

[Why & How]
Link hpd status is set during link detection process via dpia_query_hpd_status(),
doesn't need to explicitly set it during outbox irq. Remove it.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 52fbd5ec7f8d..9e9ec74b27b0 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -862,7 +862,6 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 	struct dmcub_trace_buf_entry entry = { 0 };
 	u32 count = 0;
 	struct dmub_hpd_work *dmub_hpd_wrk;
-	struct dc_link *plink = NULL;
 	static const char *const event_type[] = {
 		"NO_DATA",
 		"AUX_REPLY",
@@ -918,13 +917,6 @@ static void dm_dmub_outbox1_low_irq(void *interrupt_params)
 				}
 				INIT_WORK(&dmub_hpd_wrk->handle_hpd_work, dm_handle_hpd_work);
 				dmub_hpd_wrk->adev = adev;
-				if (notify.type == DMUB_NOTIFICATION_HPD) {
-					plink = adev->dm.dc->links[notify.link_index];
-					if (plink) {
-						plink->hpd_status =
-							notify.hpd_status == DP_HPD_PLUG;
-					}
-				}
 				queue_work(adev->dm.delayed_hpd_wq, &dmub_hpd_wrk->handle_hpd_work);
 			} else {
 				dm->dmub_callback[notify.type](adev, &notify);
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 34/67] drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAX
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (32 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 33/67] drm/amd/display: Defer the setting of link hpd status " Zaeem Mohamed
@ 2024-06-06 21:55 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 35/67] drm/amd/display: Change dram_clock_latency to 34us for dcn351 Zaeem Mohamed
                   ` (32 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:55 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

From: Wayne Lin <wayne.lin@amd.com>

[Why & How]
It actually exposes '6' types in enum dmub_notification_type. Not 5. Using smaller
number to create array dmub_callback & dmub_thread_offload has potential to access
item out of array bound. Fix it.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 94fc4c15d2db..ca1867702742 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -50,7 +50,7 @@
 
 #define AMDGPU_DM_MAX_NUM_EDP 2
 
-#define AMDGPU_DMUB_NOTIFICATION_MAX 5
+#define AMDGPU_DMUB_NOTIFICATION_MAX 6
 
 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A
 #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 35/67] drm/amd/display: Change dram_clock_latency to 34us for dcn351
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (33 preceding siblings ...)
  2024-06-06 21:55 ` [PATCH 34/67] drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAX Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 36/67] drm/amd/display: change dram_clock_latency to 34us for dcn35 Zaeem Mohamed
                   ` (31 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Daniel Miess, Nicholas Kazlauskas, Zaeem Mohamed

From: Daniel Miess <daniel.miess@amd.com>

[Why]
Intermittent underflow observed when using 4k144 display on
dcn351

[How]
Update dram_clock_change_latency_us from 11.72us to 34us

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
index e4f333d4fb54..a201dbb743d7 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c
@@ -215,7 +215,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = {
 	.urgent_latency_pixel_data_only_us = 4.0,
 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 	.urgent_latency_vm_data_only_us = 4.0,
-	.dram_clock_change_latency_us = 11.72,
+	.dram_clock_change_latency_us = 34,
 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 36/67] drm/amd/display: change dram_clock_latency to 34us for dcn35
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (34 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 35/67] drm/amd/display: Change dram_clock_latency to 34us for dcn351 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 37/67] drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_compute Zaeem Mohamed
                   ` (30 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Paul Hsieh, Nicholas Kazlauskas, Zaeem Mohamed

From: Paul Hsieh <paul.hsieh@amd.com>

[Why & How]
Current DRAM setting would cause underflow on customer platform.
Modify dram_clock_change_latency_us from 11.72 to 34.0 us as per recommendation from HW team

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Paul Hsieh <paul.hsieh@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
index 60f251cf973b..beed7adbbd43 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn35/dcn35_fpu.c
@@ -177,7 +177,7 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_5_soc = {
 	.urgent_latency_pixel_data_only_us = 4.0,
 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 	.urgent_latency_vm_data_only_us = 4.0,
-	.dram_clock_change_latency_us = 11.72,
+	.dram_clock_change_latency_us = 34.0,
 	.urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 	.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 	.urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 37/67] drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_compute
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (35 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 36/67] drm/amd/display: change dram_clock_latency to 34us for dcn35 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 38/67] drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode() Zaeem Mohamed
                   ` (29 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

From: Wayne Lin <wayne.lin@amd.com>

[Why]
When unplug one of monitors connected after mst hub, encounter null pointer dereference.

It's due to dc_sink get released immediately in early_unregister() or detect_ctx(). When
commit new state which directly referring to info stored in dc_sink will cause null pointer
dereference.

[how]
Remove redundant checking condition. Relevant condition should already be covered by checking
if dsc_aux is null or not. Also reset dsc_aux to NULL when the connector is disconnected.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c  | 12 ++++--------
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index ac60f688660a..f60d55c17fb4 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -182,6 +182,8 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector)
 		dc_sink_release(dc_sink);
 		aconnector->dc_sink = NULL;
 		aconnector->edid = NULL;
+		aconnector->dsc_aux = NULL;
+		port->passthrough_aux = NULL;
 	}
 
 	aconnector->mst_status = MST_STATUS_DEFAULT;
@@ -498,6 +500,8 @@ dm_dp_mst_detect(struct drm_connector *connector,
 		dc_sink_release(aconnector->dc_sink);
 		aconnector->dc_sink = NULL;
 		aconnector->edid = NULL;
+		aconnector->dsc_aux = NULL;
+		port->passthrough_aux = NULL;
 
 		amdgpu_dm_set_mst_status(&aconnector->mst_status,
 			MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD,
@@ -1238,14 +1242,6 @@ static bool is_dsc_need_re_compute(
 		if (!aconnector || !aconnector->dsc_aux)
 			continue;
 
-		/*
-		 *	check if cached virtual MST DSC caps are available and DSC is supported
-		 *	as per specifications in their Virtual DPCD registers.
-		*/
-		if (!(aconnector->dc_sink->dsc_caps.dsc_dec_caps.is_dsc_supported ||
-			aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))
-			continue;
-
 		stream_on_link[new_stream_on_link_num] = aconnector;
 		new_stream_on_link_num++;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 38/67] drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (36 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 37/67] drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_compute Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 39/67] drm/amd/display: define abm debug interface Zaeem Mohamed
                   ` (28 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Zaeem Mohamed

From: Wayne Lin <wayne.lin@amd.com>

[Why]
dm_dp_mst_is_port_support_mode() is a bit not following the original design rule and cause
light up issue with multiple 4k monitors after mst dsc hub.

[How]
Refactor function dm_dp_mst_is_port_support_mode() a bit to solve the light up issue.

Reviewed-by: Jerry Zuo <jerry.zuo@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
---
 .../display/amdgpu_dm/amdgpu_dm_mst_types.c   | 236 +++++++++++-------
 1 file changed, 148 insertions(+), 88 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index f60d55c17fb4..0edaae30900f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1597,111 +1597,171 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream,
 }
 #endif
 
+#if defined(CONFIG_DRM_AMD_DC_FP)
+static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw)
+{
+	uint32_t total_data_bw_efficiency_x10000 = 0;
+	uint32_t link_rate_per_lane_kbps = 0;
+	enum dc_link_rate link_rate;
+	union lane_count_set lane_count;
+	u8 dp_link_encoding;
+	u8 link_bw_set = 0;
+
+	*cur_link_bw = 0;
+
+	if (drm_dp_dpcd_read(aux, DP_MAIN_LINK_CHANNEL_CODING_SET, &dp_link_encoding, 1) != 1 ||
+		drm_dp_dpcd_read(aux, DP_LANE_COUNT_SET, &lane_count.raw, 1) != 1 ||
+		drm_dp_dpcd_read(aux, DP_LINK_BW_SET, &link_bw_set, 1) != 1)
+		return false;
+
+	switch (dp_link_encoding) {
+	case DP_8b_10b_ENCODING:
+		link_rate = link_bw_set;
+		link_rate_per_lane_kbps = link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE;
+		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000;
+		total_data_bw_efficiency_x10000 /= 100;
+		total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100;
+		break;
+	case DP_128b_132b_ENCODING:
+		switch (link_bw_set) {
+		case DP_LINK_BW_10:
+			link_rate = LINK_RATE_UHBR10;
+			break;
+		case DP_LINK_BW_13_5:
+			link_rate = LINK_RATE_UHBR13_5;
+			break;
+		case DP_LINK_BW_20:
+			link_rate = LINK_RATE_UHBR20;
+			break;
+		default:
+			return false;
+		}
+
+		link_rate_per_lane_kbps = link_rate * 10000;
+		total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_128b_132b_x10000;
+		break;
+	default:
+		return false;
+	}
+
+	*cur_link_bw = link_rate_per_lane_kbps * lane_count.bits.LANE_COUNT_SET / 10000 * total_data_bw_efficiency_x10000;
+	return true;
+}
+#endif
+
 enum dc_status dm_dp_mst_is_port_support_mode(
 	struct amdgpu_dm_connector *aconnector,
 	struct dc_stream_state *stream)
 {
-	int branch_max_throughput_mps = 0;
 #if defined(CONFIG_DRM_AMD_DC_FP)
+	int branch_max_throughput_mps = 0;
 	struct dc_link_settings cur_link_settings;
-	int pbn;
-	unsigned int end_to_end_bw_in_kbps = 0;
-	unsigned int upper_link_bw_in_kbps = 0, down_link_bw_in_kbps = 0;
+	uint32_t end_to_end_bw_in_kbps = 0;
+	uint32_t root_link_bw_in_kbps = 0;
+	uint32_t virtual_channel_bw_in_kbps = 0;
 	struct dc_dsc_bw_range bw_range = {0};
 	struct dc_dsc_config_options dsc_options = {0};
+	uint32_t stream_kbps;
 
-	/*
-	 * Consider the case with the depth of the mst topology tree is equal or less than 2
-	 * A. When dsc bitstream can be transmitted along the entire path
-	 *    1. dsc is possible between source and branch/leaf device (common dsc params is possible), AND
-	 *    2. dsc passthrough supported at MST branch, or
-	 *    3. dsc decoding supported at leaf MST device
-	 *    Use maximum dsc compression as bw constraint
-	 * B. When dsc bitstream cannot be transmitted along the entire path
-	 *    Use native bw as bw constraint
+	/* DSC unnecessary case
+	 * Check if timing could be supported within end-to-end BW
 	 */
-	if (is_dsc_common_config_possible(stream, &bw_range) &&
-	   (aconnector->mst_output_port->passthrough_aux ||
-	    aconnector->dsc_aux == &aconnector->mst_output_port->aux)) {
-		cur_link_settings = stream->link->verified_link_cap;
-		upper_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings);
-		down_link_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
-
-		/* pick the end to end bw bottleneck */
-		end_to_end_bw_in_kbps = min(upper_link_bw_in_kbps, down_link_bw_in_kbps);
-
-		if (end_to_end_bw_in_kbps < bw_range.min_kbps) {
-			DRM_DEBUG_DRIVER("maximum dsc compression cannot fit into end-to-end bandwidth\n");
-			return DC_FAIL_BANDWIDTH_VALIDATE;
-		}
+	stream_kbps =
+		dc_bandwidth_in_kbps_from_timing(&stream->timing,
+			dc_link_get_highest_encoding_format(stream->link));
+	cur_link_settings = stream->link->verified_link_cap;
+	root_link_bw_in_kbps = dc_link_bandwidth_kbps(aconnector->dc_link, &cur_link_settings);
+	virtual_channel_bw_in_kbps = kbps_from_pbn(aconnector->mst_output_port->full_pbn);
+
+	/* pick the end to end bw bottleneck */
+	end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
+
+	if (stream_kbps <= end_to_end_bw_in_kbps) {
+		DRM_DEBUG_DRIVER("No DSC needed. End-to-end bw sufficient.");
+		return DC_OK;
+	}
 
-		if (end_to_end_bw_in_kbps < bw_range.stream_kbps) {
-			dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
-			dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
-			if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
-					&stream->sink->dsc_caps.dsc_dec_caps,
-					&dsc_options,
-					end_to_end_bw_in_kbps,
-					&stream->timing,
-					dc_link_get_highest_encoding_format(stream->link),
-					&stream->timing.dsc_cfg)) {
-				stream->timing.flags.DSC = 1;
-				DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc and dsc config found\n");
-			} else {
-				DRM_DEBUG_DRIVER("end-to-end bandwidth require dsc but dsc config not found\n");
-				return DC_FAIL_BANDWIDTH_VALIDATE;
+	/*DSC necessary case*/
+	if (!aconnector->dsc_aux)
+		return DC_FAIL_BANDWIDTH_VALIDATE;
+
+	if (is_dsc_common_config_possible(stream, &bw_range)) {
+
+		/*capable of dsc passthough. dsc bitstream along the entire path*/
+		if (aconnector->mst_output_port->passthrough_aux) {
+			if (bw_range.min_kbps > end_to_end_bw_in_kbps) {
+				DRM_DEBUG_DRIVER("DSC passthrough. Max dsc compression can't fit into end-to-end bw\n");
+ 			return DC_FAIL_BANDWIDTH_VALIDATE;
 			}
-		}
-	} else {
-		/* Check if mode could be supported within max slot
-		 * number of current mst link and full_pbn of mst links.
-		 */
-		int pbn_div, slot_num, max_slot_num;
-		enum dc_link_encoding_format link_encoding;
-		uint32_t stream_kbps =
-			dc_bandwidth_in_kbps_from_timing(&stream->timing,
-				dc_link_get_highest_encoding_format(stream->link));
-
-		pbn = kbps_to_peak_pbn(stream_kbps);
-		pbn_div = dm_mst_get_pbn_divider(stream->link);
-		slot_num = DIV_ROUND_UP(pbn, pbn_div);
-
-		link_encoding = dc_link_get_highest_encoding_format(stream->link);
-		if (link_encoding == DC_LINK_ENCODING_DP_8b_10b)
-			max_slot_num = 63;
-		else if (link_encoding == DC_LINK_ENCODING_DP_128b_132b)
-			max_slot_num = 64;
-		else {
-			DRM_DEBUG_DRIVER("Invalid link encoding format\n");
+		} else {
+			/*dsc bitstream decoded at the dp last link*/
+			struct drm_dp_mst_port *immediate_upstream_port = NULL;
+			uint32_t end_link_bw = 0;
+
+			/*Get last DP link BW capability*/
+			if (dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw)) {
+				if (stream_kbps > end_link_bw) {
+					DRM_DEBUG_DRIVER("DSC decode at last link. Mode required bw can't fit into available bw\n");
+					return DC_FAIL_BANDWIDTH_VALIDATE;
+				}
+			}
+
+			/*Get virtual channel bandwidth between source and the link before the last link*/
+			if (aconnector->mst_output_port->parent->port_parent)
+				immediate_upstream_port = aconnector->mst_output_port->parent->port_parent;
+
+			if (immediate_upstream_port) {
+				virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn);
+				virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps);
+				if (bw_range.min_kbps > virtual_channel_bw_in_kbps) {
+					DRM_DEBUG_DRIVER("DSC decode at last link. Max dsc compression can't fit into MST available bw\n");
+					return DC_FAIL_BANDWIDTH_VALIDATE;
+				}
+			}
+	 	}
+
+		/*Confirm if we can obtain dsc config*/
+		dc_dsc_get_default_config_option(stream->link->dc, &dsc_options);
+		dsc_options.max_target_bpp_limit_override_x16 = aconnector->base.display_info.max_dsc_bpp * 16;
+		if (dc_dsc_compute_config(stream->sink->ctx->dc->res_pool->dscs[0],
+				&stream->sink->dsc_caps.dsc_dec_caps,
+				&dsc_options,
+				end_to_end_bw_in_kbps,
+				&stream->timing,
+				dc_link_get_highest_encoding_format(stream->link),
+				&stream->timing.dsc_cfg)) {
+			stream->timing.flags.DSC = 1;
+			DRM_DEBUG_DRIVER("Require dsc and dsc config found\n");
+		} else {
+			DRM_DEBUG_DRIVER("Require dsc but can't find appropriate dsc config\n");
 			return DC_FAIL_BANDWIDTH_VALIDATE;
 		}
 
-		if (slot_num > max_slot_num ||
-			pbn > aconnector->mst_output_port->full_pbn) {
-			DRM_DEBUG_DRIVER("Mode can not be supported within mst links!");
-			return DC_FAIL_BANDWIDTH_VALIDATE;
+		/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
+		switch (stream->timing.pixel_encoding) {
+		case PIXEL_ENCODING_RGB:
+		case PIXEL_ENCODING_YCBCR444:
+			branch_max_throughput_mps =
+				aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
+			break;
+		case PIXEL_ENCODING_YCBCR422:
+		case PIXEL_ENCODING_YCBCR420:
+			branch_max_throughput_mps =
+				aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
+			break;
+		default:
+			break;
 		}
-	}
-	/* check is mst dsc output bandwidth branch_overall_throughput_0_mps */
-	switch (stream->timing.pixel_encoding) {
-	case PIXEL_ENCODING_RGB:
-	case PIXEL_ENCODING_YCBCR444:
-		branch_max_throughput_mps =
-			aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_0_mps;
-		break;
-	case PIXEL_ENCODING_YCBCR422:
-	case PIXEL_ENCODING_YCBCR420:
-		branch_max_throughput_mps =
-			aconnector->dc_sink->dsc_caps.dsc_dec_caps.branch_overall_throughput_1_mps;
-		break;
-	default:
-		break;
-	}
-#endif
 
-	if (branch_max_throughput_mps != 0 &&
-		((stream->timing.pix_clk_100hz / 10) >  branch_max_throughput_mps * 1000))
+		if (branch_max_throughput_mps != 0 &&
+			((stream->timing.pix_clk_100hz / 10) >  branch_max_throughput_mps * 1000)) {
+			DRM_DEBUG_DRIVER("DSC is required but max throughput mps fails");
+ 		return DC_FAIL_BANDWIDTH_VALIDATE;
+		}
+	} else {
+		DRM_DEBUG_DRIVER("DSC is required but can't find common dsc config.");
 		return DC_FAIL_BANDWIDTH_VALIDATE;
-
+	}
+#endif
 	return DC_OK;
 }
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 39/67] drm/amd/display: define abm debug interface
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (37 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 38/67] drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode() Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 40/67] drm/amd/display: Introduce overlay cursor mode Zaeem Mohamed
                   ` (27 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Josip Pavic, Anthony Koo, Zaeem Mohamed

From: Josip Pavic <josip.pavic@amd.com>

[Why & How]
Define debug interface to dmub for reading back abm data.

Reviewed-by: Anthony Koo <anthony.koo@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Josip Pavic <josip.pavic@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 60 +++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 7fea9bec7b64..87f2e4e38f9a 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -3960,6 +3960,11 @@ enum dmub_cmd_abm_type {
 	 * Set ABM Events
 	 */
 	DMUB_CMD__ABM_SET_EVENT	= 9,
+
+	/**
+	 * Get the current ACE curve.
+	 */
+	DMUB_CMD__ABM_GET_ACE_CURVE = 10,
 };
 
 struct abm_ace_curve {
@@ -4488,6 +4493,55 @@ struct dmub_rb_cmd_abm_query_caps {
 	} data;
 };
 
+/**
+ * enum dmub_abm_ace_curve_type - ACE curve type.
+ */
+enum dmub_abm_ace_curve_type {
+	/**
+	 * ACE curve as defined by the SW layer.
+	 */
+	ABM_ACE_CURVE_TYPE__SW = 0,
+	/**
+	 * ACE curve as defined by the SW to HW translation interface layer.
+	 */
+	ABM_ACE_CURVE_TYPE__SW_IF = 1,
+};
+
+/**
+ * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
+ */
+struct dmub_rb_cmd_abm_get_ace_curve {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+
+	/**
+	 * Address where ACE curve should be copied.
+	 */
+	union dmub_addr dest;
+
+	/**
+	 * Type of ACE curve being queried.
+	 */
+	enum dmub_abm_ace_curve_type ace_type;
+
+	/**
+	 * Indirect buffer length.
+	 */
+	uint16_t bytes;
+
+	/**
+	 * eDP panel instance.
+	 */
+	uint8_t panel_inst;
+
+	/**
+	 * Explicit padding to 4 byte boundary.
+	 */
+	uint8_t pad;
+};
+
 /**
  * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
  */
@@ -4521,6 +4575,7 @@ struct dmub_rb_cmd_abm_save_restore {
 /**
  * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command.
  */
+
 struct dmub_cmd_abm_set_event_data {
 
 	/**
@@ -5102,6 +5157,11 @@ union dmub_rb_cmd {
 	 */
 	struct dmub_rb_cmd_abm_query_caps abm_query_caps;
 
+	/**
+	 * Definition of a DMUB_CMD__ABM_GET_ACE_CURVE command.
+	 */
+	struct dmub_rb_cmd_abm_get_ace_curve abm_get_ace_curve;
+
 	/**
 	 * Definition of a DMUB_CMD__ABM_SET_EVENT command.
 	 */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 40/67] drm/amd/display: Introduce overlay cursor mode
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (38 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 39/67] drm/amd/display: define abm debug interface Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 41/67] drm/amd/display: Move PRIMARY plane zpos higher Zaeem Mohamed
                   ` (26 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Leo Li, Harry Wentland, Zaeem Mohamed, Pekka Paalanen

From: Leo Li <sunpeng.li@amd.com>

[Why]

DCN is the display hardware for amdgpu. DRM planes are backed by DCN
hardware pipes, which carry pixel data from one end (memory), to the
other (output encoder).

Each DCN pipe has the ability to blend in a cursor early on in the
pipeline. In other words, there are no dedicated cursor planes in DCN,
which makes cursor behavior somewhat unintuitive for compositors.

For example, if the cursor is in RGB format, but the top-most DRM plane
is in YUV format, DCN will not be able to blend them. Because of this,
amdgpu_dm rejects all configurations where a cursor needs to be enabled
on top of a YUV formatted plane.

From a compositor's perspective, when computing an allocation for
hardware plane offloading, this cursor-on-yuv configuration result in an
atomic test failure. Since the failure reason is not obvious at all,
compositors will likely fall back to full rendering, which is not ideal.

Instead, amdgpu_dm can try to accommodate the cursor-on-yuv
configuration by opportunistically reserving a separate DCN pipe just
for the cursor. We can refer to this as "overlay cursor mode". It is
contrasted with "native cursor mode", where the native DCN per-pipe
cursor is used.

[How]

On each crtc, compute whether the cursor plane should be enabled in
overlay mode. If it is, mark the CRTC as requesting overlay cursor mode.

Overlay cursor should be enabled whenever there exists a underlying
plane that has YUV format, or is scaled differently than the cursor. It
should also be enabled if there is no underlying plane, or if underlying
planes do not cover the entire CRTC.

During DC validation, attempt to enable a separate DCN pipe for the
cursor if it's in overlay mode. If that fails, or if no overlay mode is
requested, then fallback to native mode.

v2:
* Update commit message for when overlay cursor should be enabled
* Also consider scale and no-underlying-plane case (cursor on crtc bg)
* Consider all underlying planes when determinig overlay/native, not
  just the plane immediately beneath the cursor, as it may not cover the
  entire CRTC.
* Fix typo s/decending/descending/
* Force native cursor on pre-DCN hardware

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 490 +++++++++++++-----
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h |   7 +
 .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |   1 +
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   |  13 +-
 4 files changed, 389 insertions(+), 122 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 9e9ec74b27b0..6697ee9b3d72 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -8756,8 +8756,24 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 	 * Disable the cursor first if we're disabling all the planes.
 	 * It'll remain on the screen after the planes are re-enabled
 	 * if we don't.
+	 *
+	 * If the cursor is transitioning from native to overlay mode, the
+	 * native cursor needs to be disabled first.
 	 */
-	if (acrtc_state->active_planes == 0)
+	if (acrtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE &&
+	    dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
+		struct dc_cursor_position cursor_position = {0};
+
+		if (!dc_stream_set_cursor_position(acrtc_state->stream,
+						   &cursor_position))
+			drm_err(dev, "DC failed to disable native cursor\n");
+
+		bundle->stream_update.cursor_position =
+				&acrtc_state->stream->cursor_position;
+	}
+
+	if (acrtc_state->active_planes == 0 &&
+	    dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
 		amdgpu_dm_commit_cursors(state);
 
 	/* update planes when needed */
@@ -8771,7 +8787,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		struct dm_plane_state *dm_new_plane_state = to_dm_plane_state(new_plane_state);
 
 		/* Cursor plane is handled after stream updates */
-		if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+		if (plane->type == DRM_PLANE_TYPE_CURSOR &&
+		    acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE) {
 			if ((fb && crtc == pcrtc) ||
 			    (old_plane_state->fb && old_plane_state->crtc == pcrtc)) {
 				cursor_update = true;
@@ -9127,7 +9144,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 	 * to be disabling a single plane - those pipes are being disabled.
 	 */
 	if (acrtc_state->active_planes &&
-	    (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0))
+	    (!updated_planes_and_streams || amdgpu_ip_version(dm->adev, DCE_HWIP, 0) == 0) &&
+	    acrtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE)
 		amdgpu_dm_commit_cursors(state);
 
 cleanup:
@@ -10445,7 +10463,8 @@ static bool should_reset_plane(struct drm_atomic_state *state,
 {
 	struct drm_plane *other;
 	struct drm_plane_state *old_other_state, *new_other_state;
-	struct drm_crtc_state *new_crtc_state;
+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+	struct dm_crtc_state *old_dm_crtc_state, *new_dm_crtc_state;
 	struct amdgpu_device *adev = drm_to_adev(plane->dev);
 	int i;
 
@@ -10467,10 +10486,24 @@ static bool should_reset_plane(struct drm_atomic_state *state,
 
 	new_crtc_state =
 		drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
+	old_crtc_state =
+		drm_atomic_get_old_crtc_state(state, old_plane_state->crtc);
 
 	if (!new_crtc_state)
 		return true;
 
+	/*
+	 * A change in cursor mode means a new dc pipe needs to be acquired or
+	 * released from the state
+	 */
+	old_dm_crtc_state = to_dm_crtc_state(old_crtc_state);
+	new_dm_crtc_state = to_dm_crtc_state(new_crtc_state);
+	if (plane->type == DRM_PLANE_TYPE_CURSOR &&
+	    old_dm_crtc_state != NULL &&
+	    old_dm_crtc_state->cursor_mode != new_dm_crtc_state->cursor_mode) {
+		return true;
+	}
+
 	/* CRTC Degamma changes currently require us to recreate planes. */
 	if (new_crtc_state->color_mgmt_changed)
 		return true;
@@ -10622,6 +10655,68 @@ static int dm_check_cursor_fb(struct amdgpu_crtc *new_acrtc,
 	return 0;
 }
 
+/*
+ * Helper function for checking the cursor in native mode
+ */
+static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc,
+					struct drm_plane *plane,
+					struct drm_plane_state *new_plane_state,
+					bool enable)
+{
+
+	struct amdgpu_crtc *new_acrtc;
+	int ret;
+
+	if (!enable || !new_plane_crtc ||
+	    drm_atomic_plane_disabling(plane->state, new_plane_state))
+		return 0;
+
+	new_acrtc = to_amdgpu_crtc(new_plane_crtc);
+
+	if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
+		DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
+		return -EINVAL;
+	}
+
+	if (new_plane_state->fb) {
+		ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
+						new_plane_state->fb);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static bool dm_should_update_native_cursor(struct drm_atomic_state *state,
+					   struct drm_crtc *old_plane_crtc,
+					   struct drm_crtc *new_plane_crtc,
+					   bool enable)
+{
+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
+
+	if (!enable) {
+		if (old_plane_crtc == NULL)
+			return true;
+
+		old_crtc_state = drm_atomic_get_old_crtc_state(
+			state, old_plane_crtc);
+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+
+		return dm_old_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;
+	} else {
+		if (new_plane_crtc == NULL)
+			return true;
+
+		new_crtc_state = drm_atomic_get_new_crtc_state(
+			state, new_plane_crtc);
+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+
+		return dm_new_crtc_state->cursor_mode == DM_CURSOR_NATIVE_MODE;
+	}
+}
+
 static int dm_update_plane_state(struct dc *dc,
 				 struct drm_atomic_state *state,
 				 struct drm_plane *plane,
@@ -10637,8 +10732,7 @@ static int dm_update_plane_state(struct dc *dc,
 	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
 	struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state;
 	struct dm_plane_state *dm_new_plane_state, *dm_old_plane_state;
-	struct amdgpu_crtc *new_acrtc;
-	bool needs_reset;
+	bool needs_reset, update_native_cursor;
 	int ret = 0;
 
 
@@ -10647,24 +10741,16 @@ static int dm_update_plane_state(struct dc *dc,
 	dm_new_plane_state = to_dm_plane_state(new_plane_state);
 	dm_old_plane_state = to_dm_plane_state(old_plane_state);
 
-	if (plane->type == DRM_PLANE_TYPE_CURSOR) {
-		if (!enable || !new_plane_crtc ||
-			drm_atomic_plane_disabling(plane->state, new_plane_state))
-			return 0;
-
-		new_acrtc = to_amdgpu_crtc(new_plane_crtc);
+	update_native_cursor = dm_should_update_native_cursor(state,
+							      old_plane_crtc,
+							      new_plane_crtc,
+							      enable);
 
-		if (new_plane_state->src_x != 0 || new_plane_state->src_y != 0) {
-			DRM_DEBUG_ATOMIC("Cropping not supported for cursor plane\n");
-			return -EINVAL;
-		}
-
-		if (new_plane_state->fb) {
-			ret = dm_check_cursor_fb(new_acrtc, new_plane_state,
-						 new_plane_state->fb);
-			if (ret)
-				return ret;
-		}
+	if (plane->type == DRM_PLANE_TYPE_CURSOR && update_native_cursor) {
+		ret = dm_check_native_cursor_state(new_plane_crtc, plane,
+						    new_plane_state, enable);
+		if (ret)
+			return ret;
 
 		return 0;
 	}
@@ -10730,20 +10816,14 @@ static int dm_update_plane_state(struct dc *dc,
 
 		ret = amdgpu_dm_plane_helper_check_state(new_plane_state, new_crtc_state);
 		if (ret)
-			return ret;
+			goto out;
 
 		WARN_ON(dm_new_plane_state->dc_state);
 
 		dc_new_plane_state = dc_create_plane_state(dc);
-		if (!dc_new_plane_state)
-			return -ENOMEM;
-
-		/* Block top most plane from being a video plane */
-		if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
-			if (amdgpu_dm_plane_is_video_format(new_plane_state->fb->format->format) && *is_top_most_overlay)
-				return -EINVAL;
-
-			*is_top_most_overlay = false;
+		if (!dc_new_plane_state) {
+			ret = -ENOMEM;
+			goto out;
 		}
 
 		DRM_DEBUG_ATOMIC("Enabling DRM plane: %d on DRM crtc %d\n",
@@ -10756,13 +10836,13 @@ static int dm_update_plane_state(struct dc *dc,
 			new_crtc_state);
 		if (ret) {
 			dc_plane_state_release(dc_new_plane_state);
-			return ret;
+			goto out;
 		}
 
 		ret = dm_atomic_get_state(state, &dm_state);
 		if (ret) {
 			dc_plane_state_release(dc_new_plane_state);
-			return ret;
+			goto out;
 		}
 
 		/*
@@ -10779,7 +10859,8 @@ static int dm_update_plane_state(struct dc *dc,
 				dm_state->context)) {
 
 			dc_plane_state_release(dc_new_plane_state);
-			return -EINVAL;
+			ret = -EINVAL;
+			goto out;
 		}
 
 		dm_new_plane_state->dc_state = dc_new_plane_state;
@@ -10794,6 +10875,16 @@ static int dm_update_plane_state(struct dc *dc,
 		*lock_and_validation_needed = true;
 	}
 
+out:
+	/* If enabling cursor overlay failed, attempt fallback to native mode */
+	if (enable && ret == -EINVAL && plane->type == DRM_PLANE_TYPE_CURSOR) {
+		ret = dm_check_native_cursor_state(new_plane_crtc, plane,
+						    new_plane_state, enable);
+		if (ret)
+			return ret;
+
+		dm_new_crtc_state->cursor_mode = DM_CURSOR_NATIVE_MODE;
+	}
 
 	return ret;
 }
@@ -10827,99 +10918,64 @@ dm_get_plane_scale(struct drm_plane_state *plane_state,
 	*out_plane_scale_h = plane_state->crtc_h * 1000 / plane_src_h;
 }
 
-static int dm_check_crtc_cursor(struct drm_atomic_state *state,
-				struct drm_crtc *crtc,
-				struct drm_crtc_state *new_crtc_state)
+/*
+ * The normalized_zpos value cannot be used by this iterator directly. It's only
+ * calculated for enabled planes, potentially causing normalized_zpos collisions
+ * between enabled/disabled planes in the atomic state. We need a unique value
+ * so that the iterator will not generate the same object twice, or loop
+ * indefinitely.
+ */
+static inline struct __drm_planes_state *__get_next_zpos(
+	struct drm_atomic_state *state,
+	struct __drm_planes_state *prev)
 {
-	struct drm_plane *cursor = crtc->cursor, *plane, *underlying;
-	struct drm_plane_state *old_plane_state, *new_plane_state;
-	struct drm_plane_state *new_cursor_state, *new_underlying_state;
-	int i;
-	int cursor_scale_w, cursor_scale_h, underlying_scale_w, underlying_scale_h;
-	bool any_relevant_change = false;
-
-	/* On DCE and DCN there is no dedicated hardware cursor plane. We get a
-	 * cursor per pipe but it's going to inherit the scaling and
-	 * positioning from the underlying pipe. Check the cursor plane's
-	 * blending properties match the underlying planes'.
-	 */
-
-	/* If no plane was enabled or changed scaling, no need to check again */
-	for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) {
-		int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
-
-		if (!new_plane_state || !new_plane_state->fb || new_plane_state->crtc != crtc)
-			continue;
-
-		if (!old_plane_state || !old_plane_state->fb || old_plane_state->crtc != crtc) {
-			any_relevant_change = true;
-			break;
-		}
-
-		if (new_plane_state->fb == old_plane_state->fb &&
-		    new_plane_state->crtc_w == old_plane_state->crtc_w &&
-		    new_plane_state->crtc_h == old_plane_state->crtc_h)
-			continue;
-
-		dm_get_plane_scale(new_plane_state, &new_scale_w, &new_scale_h);
-		dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
+	unsigned int highest_zpos = 0, prev_zpos = 256;
+	uint32_t highest_id = 0, prev_id = UINT_MAX;
+	struct drm_plane_state *new_plane_state;
+	struct drm_plane *plane;
+	int i, highest_i = -1;
 
-		if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
-			any_relevant_change = true;
-			break;
-		}
+	if (prev != NULL) {
+		prev_zpos = prev->new_state->zpos;
+		prev_id = prev->ptr->base.id;
 	}
 
-	if (!any_relevant_change)
-		return 0;
-
-	new_cursor_state = drm_atomic_get_plane_state(state, cursor);
-	if (IS_ERR(new_cursor_state))
-		return PTR_ERR(new_cursor_state);
-
-	if (!new_cursor_state->fb)
-		return 0;
-
-	dm_get_plane_scale(new_cursor_state, &cursor_scale_w, &cursor_scale_h);
-
-	/* Need to check all enabled planes, even if this commit doesn't change
-	 * their state
-	 */
-	i = drm_atomic_add_affected_planes(state, crtc);
-	if (i)
-		return i;
-
-	for_each_new_plane_in_state_reverse(state, underlying, new_underlying_state, i) {
-		/* Narrow down to non-cursor planes on the same CRTC as the cursor */
-		if (new_underlying_state->crtc != crtc || underlying == crtc->cursor)
-			continue;
-
-		/* Ignore disabled planes */
-		if (!new_underlying_state->fb)
+	for_each_new_plane_in_state(state, plane, new_plane_state, i) {
+		/* Skip planes with higher zpos than the previously returned */
+		if (new_plane_state->zpos > prev_zpos ||
+		    (new_plane_state->zpos == prev_zpos &&
+		     plane->base.id >= prev_id))
 			continue;
 
-		dm_get_plane_scale(new_underlying_state,
-				   &underlying_scale_w, &underlying_scale_h);
-
-		if (cursor_scale_w != underlying_scale_w ||
-		    cursor_scale_h != underlying_scale_h) {
-			drm_dbg_atomic(crtc->dev,
-				       "Cursor [PLANE:%d:%s] scaling doesn't match underlying [PLANE:%d:%s]\n",
-				       cursor->base.id, cursor->name, underlying->base.id, underlying->name);
-			return -EINVAL;
+		/* Save the index of the plane with highest zpos */
+		if (new_plane_state->zpos > highest_zpos ||
+		    (new_plane_state->zpos == highest_zpos &&
+		     plane->base.id > highest_id)) {
+			highest_zpos = new_plane_state->zpos;
+			highest_id = plane->base.id;
+			highest_i = i;
 		}
-
-		/* If this plane covers the whole CRTC, no need to check planes underneath */
-		if (new_underlying_state->crtc_x <= 0 &&
-		    new_underlying_state->crtc_y <= 0 &&
-		    new_underlying_state->crtc_x + new_underlying_state->crtc_w >= new_crtc_state->mode.hdisplay &&
-		    new_underlying_state->crtc_y + new_underlying_state->crtc_h >= new_crtc_state->mode.vdisplay)
-			break;
 	}
 
-	return 0;
+	if (highest_i < 0)
+		return NULL;
+
+	return &state->planes[highest_i];
 }
 
+/*
+ * Use the uniqueness of the plane's (zpos, drm obj ID) combination to iterate
+ * by descending zpos, as read from the new plane state. This is the same
+ * ordering as defined by drm_atomic_normalize_zpos().
+ */
+#define for_each_oldnew_plane_in_descending_zpos(__state, plane, old_plane_state, new_plane_state) \
+	for (struct __drm_planes_state *__i = __get_next_zpos((__state), NULL); \
+	     __i != NULL; __i = __get_next_zpos((__state), __i))		\
+		for_each_if(((plane) = __i->ptr,				\
+			     (void)(plane) /* Only to avoid unused-but-set-variable warning */, \
+			     (old_plane_state) = __i->old_state,		\
+			     (new_plane_state) = __i->new_state, 1))
+
 static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc)
 {
 	struct drm_connector *connector;
@@ -10950,6 +11006,165 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm
 	return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr);
 }
 
+/**
+ * DOC: Cursor Modes - Native vs Overlay
+ *
+ * In native mode, the cursor uses a integrated cursor pipe within each DCN hw
+ * plane. It does not require a dedicated hw plane to enable, but it is
+ * subjected to the same z-order and scaling as the hw plane. It also has format
+ * restrictions, a RGB cursor in native mode cannot be enabled within a non-RGB
+ * hw plane.
+ *
+ * In overlay mode, the cursor uses a separate DCN hw plane, and thus has its
+ * own scaling and z-pos. It also has no blending restrictions. It lends to a
+ * cursor behavior more akin to a DRM client's expectations. However, it does
+ * occupy an extra DCN plane, and therefore will only be used if a DCN plane is
+ * available.
+ */
+
+/**
+ * dm_crtc_get_cursor_mode() - Determine the required cursor mode on crtc
+ * @adev: amdgpu device
+ * @state: DRM atomic state
+ * @dm_crtc_state: amdgpu state for the CRTC containing the cursor
+ * @cursor_mode: Returns the required cursor mode on dm_crtc_state
+ *
+ * Get whether the cursor should be enabled in native mode, or overlay mode, on
+ * the dm_crtc_state.
+ *
+ * The cursor should be enabled in overlay mode if there exists an underlying
+ * plane - on which the cursor may be blended - that is either YUV formatted, or
+ * scaled differently from the cursor.
+ *
+ * Since zpos info is required, drm_atomic_normalize_zpos must be called before
+ * calling this function.
+ *
+ * Return: 0 on success, or an error code if getting the cursor plane state
+ * failed.
+ */
+static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev,
+				   struct drm_atomic_state *state,
+				   struct dm_crtc_state *dm_crtc_state,
+				   enum amdgpu_dm_cursor_mode *cursor_mode)
+{
+	struct drm_plane_state *old_plane_state, *plane_state, *cursor_state;
+	struct drm_crtc_state *crtc_state = &dm_crtc_state->base;
+	struct drm_plane *plane;
+	bool consider_mode_change = false;
+	bool entire_crtc_covered = false;
+	bool cursor_changed = false;
+	int underlying_scale_w, underlying_scale_h;
+	int cursor_scale_w, cursor_scale_h;
+	int i;
+
+	/* Overlay cursor not supported on HW before DCN */
+	if (amdgpu_ip_version(adev, DCE_HWIP, 0) == 0) {
+		*cursor_mode = DM_CURSOR_NATIVE_MODE;
+		return 0;
+	}
+
+	/* Init cursor_mode to be the same as current */
+	*cursor_mode = dm_crtc_state->cursor_mode;
+
+	/*
+	 * Cursor mode can change if a plane's format changes, scale changes, is
+	 * enabled/disabled, or z-order changes.
+	 */
+	for_each_oldnew_plane_in_state(state, plane, old_plane_state, plane_state, i) {
+		int new_scale_w, new_scale_h, old_scale_w, old_scale_h;
+
+		/* Only care about planes on this CRTC */
+		if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0)
+			continue;
+
+		if (plane->type == DRM_PLANE_TYPE_CURSOR)
+			cursor_changed = true;
+
+		if (drm_atomic_plane_enabling(old_plane_state, plane_state) ||
+		    drm_atomic_plane_disabling(old_plane_state, plane_state) ||
+		    old_plane_state->fb->format != plane_state->fb->format) {
+			consider_mode_change = true;
+			break;
+		}
+
+		dm_get_plane_scale(plane_state, &new_scale_w, &new_scale_h);
+		dm_get_plane_scale(old_plane_state, &old_scale_w, &old_scale_h);
+		if (new_scale_w != old_scale_w || new_scale_h != old_scale_h) {
+			consider_mode_change = true;
+			break;
+		}
+	}
+
+	if (!consider_mode_change && !crtc_state->zpos_changed)
+		return 0;
+
+	/*
+	 * If no cursor change on this CRTC, and not enabled on this CRTC, then
+	 * no need to set cursor mode. This avoids needlessly locking the cursor
+	 * state.
+	 */
+	if (!cursor_changed &&
+	    !(drm_plane_mask(crtc_state->crtc->cursor) & crtc_state->plane_mask)) {
+		return 0;
+	}
+
+	cursor_state = drm_atomic_get_plane_state(state,
+						  crtc_state->crtc->cursor);
+	if (IS_ERR(cursor_state))
+		return PTR_ERR(cursor_state);
+
+	/* Cursor is disabled */
+	if (!cursor_state->fb)
+		return 0;
+
+	/* For all planes in descending z-order (all of which are below cursor
+	 * as per zpos definitions), check their scaling and format
+	 */
+	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, plane_state) {
+
+		/* Only care about non-cursor planes on this CRTC */
+		if ((drm_plane_mask(plane) & crtc_state->plane_mask) == 0 ||
+		    plane->type == DRM_PLANE_TYPE_CURSOR)
+			continue;
+
+		/* Underlying plane is YUV format - use overlay cursor */
+		if (amdgpu_dm_plane_is_video_format(plane_state->fb->format->format)) {
+			*cursor_mode = DM_CURSOR_OVERLAY_MODE;
+			return 0;
+		}
+
+		dm_get_plane_scale(plane_state,
+				   &underlying_scale_w, &underlying_scale_h);
+		dm_get_plane_scale(cursor_state,
+				   &cursor_scale_w, &cursor_scale_h);
+
+		/* Underlying plane has different scale - use overlay cursor */
+		if (cursor_scale_w != underlying_scale_w &&
+		    cursor_scale_h != underlying_scale_h) {
+			*cursor_mode = DM_CURSOR_OVERLAY_MODE;
+			return 0;
+		}
+
+		/* If this plane covers the whole CRTC, no need to check planes underneath */
+		if (plane_state->crtc_x <= 0 && plane_state->crtc_y <= 0 &&
+		    plane_state->crtc_x + plane_state->crtc_w >= crtc_state->mode.hdisplay &&
+		    plane_state->crtc_y + plane_state->crtc_h >= crtc_state->mode.vdisplay) {
+			entire_crtc_covered = true;
+			break;
+		}
+	}
+
+	/* If planes do not cover the entire CRTC, use overlay mode to enable
+	 * cursor over holes
+	 */
+	if (entire_crtc_covered)
+		*cursor_mode = DM_CURSOR_NATIVE_MODE;
+	else
+		*cursor_mode = DM_CURSOR_OVERLAY_MODE;
+
+	return 0;
+}
+
 /**
  * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.
  *
@@ -11119,6 +11334,21 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 		goto fail;
 	}
 
+	/*
+	 * Determine whether cursors on each CRTC should be enabled in native or
+	 * overlay mode.
+	 */
+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+
+		ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,
+					      &dm_new_crtc_state->cursor_mode);
+		if (ret) {
+			drm_dbg(dev, "Failed to determine cursor mode\n");
+			goto fail;
+		}
+	}
+
 	/* Remove exiting planes if they are modified */
 	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
 		if (old_plane_state->fb && new_plane_state->fb &&
@@ -11199,11 +11429,29 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 			drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc);
 	}
 
-	/* Check cursor planes scaling */
+	/* Check cursor planes restrictions */
 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
-		ret = dm_check_crtc_cursor(state, crtc, new_crtc_state);
+		enum amdgpu_dm_cursor_mode required_cursor_mode;
+
+		/* Overlay cusor not subject to native cursor restrictions */
+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+		if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE)
+			continue;
+
+		/* If HW can only do native cursor, check restrictions again */
+		ret = dm_crtc_get_cursor_mode(adev, state, dm_new_crtc_state,
+					      &required_cursor_mode);
+ 
 		if (ret) {
-			drm_dbg_atomic(dev, "dm_check_crtc_cursor() failed\n");
+			drm_dbg_driver(crtc->dev,
+				       "[CRTC:%d:%s] Checking cursor mode failed\n",
+				       crtc->base.id, crtc->name);
+			goto fail;
+		} else if (required_cursor_mode == DM_CURSOR_OVERLAY_MODE) {
+			drm_dbg_driver(crtc->dev,
+				       "[CRTC:%d:%s] Cannot enable native cursor due to scaling or YUV restrictions\n",
+				       crtc->base.id, crtc->name);
+			ret = -EINVAL;
 			goto fail;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index ca1867702742..484f1f054eb6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -834,6 +834,11 @@ struct dm_plane_state {
 	enum amdgpu_transfer_function blend_tf;
 };
 
+enum amdgpu_dm_cursor_mode {
+	DM_CURSOR_NATIVE_MODE = 0,
+	DM_CURSOR_OVERLAY_MODE,
+};
+
 struct dm_crtc_state {
 	struct drm_crtc_state base;
 	struct dc_stream_state *stream;
@@ -864,6 +869,8 @@ struct dm_crtc_state {
 	 * encoding.
 	 */
 	enum amdgpu_transfer_function regamma_tf;
+
+	enum amdgpu_dm_cursor_mode cursor_mode;
 };
 
 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index 83ea0afddda7..e16eecb146fd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -361,6 +361,7 @@ static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *cr
 	state->regamma_tf = cur->regamma_tf;
 	state->crc_skip_count = cur->crc_skip_count;
 	state->mpo_requested = cur->mpo_requested;
+	state->cursor_mode = cur->cursor_mode;
 	/* TODO Duplicate dc_stream after objects are stream object is flattened */
 
 	return &state->base;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index b339642b86c0..969fc42f9a68 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -104,7 +104,7 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state
 	*global_alpha = false;
 	*global_alpha_value = 0xff;
 
-	if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
+	if (plane_state->plane->type == DRM_PLANE_TYPE_PRIMARY)
 		return;
 
 	if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||
@@ -1190,10 +1190,21 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane,
 static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane,
 					      struct drm_atomic_state *state)
 {
+	struct drm_crtc_state *new_crtc_state;
+	struct drm_plane_state *new_plane_state;
+	struct dm_crtc_state *dm_new_crtc_state;
+
 	/* Only support async updates on cursor planes. */
 	if (plane->type != DRM_PLANE_TYPE_CURSOR)
 		return -EINVAL;
 
+	new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+	new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
+	dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+	/* Reject overlay cursors for now*/
+	if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE)
+		return -EINVAL;
+
 	return 0;
 }
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 41/67] drm/amd/display: Move PRIMARY plane zpos higher
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (39 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 40/67] drm/amd/display: Introduce overlay cursor mode Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 42/67] drm/amd/display: Remove register from DCN35 DMCUB diagnostic collection Zaeem Mohamed
                   ` (25 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Leo Li, Harry Wentland, Zaeem Mohamed, Pekka Paalanen

From: Leo Li <sunpeng.li@amd.com>

[Why]

Compositors have different ways of assigning surfaces to DRM planes for
render offloading. It may decide between various strategies: overlay,
underlay, or a mix of both (see here for more info:
https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76)

One way for compositors to implement the underlay strategy is to assign
a higher zpos to the DRM_PRIMARY plane than the DRM_OVERLAY planes,
effectively turning the DRM_OVERLAY plane into an underlay plane.

Today, amdgpu attaches an immutable zpos of 0 to the DRM_PRIMARY plane.
This however, is an arbitrary restriction. DCN pipes are general
purpose, and can be arranged in any z-order. To support compositors
using this allocation scheme, we can set a non-zero immutable zpos for
the PRIMARY, allowing the placement of OVERLAYS (mutable zpos range
0-254) beneath the PRIMARY.

[How]

Assign a zpos = #no of OVERLAY planes to the PRIMARY plane. Then, clean
up any assumptions in the driver of PRIMARY plane having the lowest
zpos.

v2: Fix typo s/decending/descending/

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Leo Li <sunpeng.li@amd.com>
Acked-by: Pekka Paalanen <pekka.paalanen@collabora.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 +++++++++++++++++--
 .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 18 +++++++---
 2 files changed, 44 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 6697ee9b3d72..dbd50a32f5c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -80,6 +80,7 @@
 #include <linux/firmware.h>
 #include <linux/component.h>
 #include <linux/dmi.h>
+#include <linux/sort.h>
 
 #include <drm/display/drm_dp_mst_helper.h>
 #include <drm/display/drm_hdmi_helper.h>
@@ -375,6 +376,20 @@ static inline void reverse_planes_order(struct dc_surface_update *array_of_surfa
 		swap(array_of_surface_update[i], array_of_surface_update[j]);
 }
 
+/*
+ * DC will program planes with their z-order determined by their ordering
+ * in the dc_surface_updates array. This comparator is used to sort them
+ * by descending zpos.
+ */
+static int dm_plane_layer_index_cmp(const void *a, const void *b)
+{
+	const struct dc_surface_update *sa = (struct dc_surface_update *)a;
+	const struct dc_surface_update *sb = (struct dc_surface_update *)b;
+
+	/* Sort by descending dc_plane layer_index (i.e. normalized_zpos) */
+	return sb->surface->layer_index - sa->surface->layer_index;
+}
+
 /**
  * update_planes_and_stream_adapter() - Send planes to be updated in DC
  *
@@ -399,7 +414,8 @@ static inline bool update_planes_and_stream_adapter(struct dc *dc,
 						    struct dc_stream_update *stream_update,
 						    struct dc_surface_update *array_of_surface_update)
 {
-	reverse_planes_order(array_of_surface_update, planes_count);
+	sort(array_of_surface_update, planes_count,
+	     sizeof(*array_of_surface_update), dm_plane_layer_index_cmp, NULL);
 
 	/*
 	 * Previous frame finished and HW is ready for optimization.
@@ -9773,6 +9789,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 		for (j = 0; j < status->plane_count; j++)
 			dummy_updates[j].surface = status->plane_states[0];
 
+		sort(dummy_updates, status->plane_count,
+		     sizeof(*dummy_updates), dm_plane_layer_index_cmp, NULL);
 
 		mutex_lock(&dm->dc_lock);
 		dc_exit_ips_for_hw_access(dm->dc);
@@ -10508,6 +10526,16 @@ static bool should_reset_plane(struct drm_atomic_state *state,
 	if (new_crtc_state->color_mgmt_changed)
 		return true;
 
+	/*
+	 * On zpos change, planes need to be reordered by removing and re-adding
+	 * them one by one to the dc state, in order of descending zpos.
+	 *
+	 * TODO: We can likely skip bandwidth validation if the only thing that
+	 * changed about the plane was it'z z-ordering.
+	 */
+	if (new_crtc_state->zpos_changed)
+		return true;
+
 	if (drm_atomic_crtc_needs_modeset(new_crtc_state))
 		return true;
 
@@ -11350,7 +11378,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 	}
 
 	/* Remove exiting planes if they are modified */
-	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
+	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
 		if (old_plane_state->fb && new_plane_state->fb &&
 		    get_mem_type(old_plane_state->fb) !=
 		    get_mem_type(new_plane_state->fb))
@@ -11395,7 +11423,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev,
 	}
 
 	/* Add new/modified planes */
-	for_each_oldnew_plane_in_state_reverse(state, plane, old_plane_state, new_plane_state, i) {
+	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {
 		ret = dm_update_plane_state(dc, state, plane,
 					    old_plane_state,
 					    new_plane_state,
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 969fc42f9a68..d9ea2cd1638f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -104,8 +104,6 @@ void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state
 	*global_alpha = false;
 	*global_alpha_value = 0xff;
 
-	if (plane_state->plane->type == DRM_PLANE_TYPE_PRIMARY)
-		return;
 
 	if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI ||
 		plane_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE) {
@@ -1709,6 +1707,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 	int res = -EPERM;
 	unsigned int supported_rotations;
 	uint64_t *modifiers = NULL;
+	unsigned int primary_zpos = dm->dc->caps.max_slave_planes;
 
 	num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats,
 							ARRAY_SIZE(formats));
@@ -1738,10 +1737,19 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 	}
 
 	if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
-		drm_plane_create_zpos_immutable_property(plane, 0);
+		/*
+		 * Allow OVERLAY planes to be used as underlays by assigning an
+		 * immutable zpos = # of OVERLAY planes to the PRIMARY plane.
+		 */
+		drm_plane_create_zpos_immutable_property(plane, primary_zpos);
 	} else if (plane->type == DRM_PLANE_TYPE_OVERLAY) {
-		unsigned int zpos = 1 + drm_plane_index(plane);
-		drm_plane_create_zpos_property(plane, zpos, 1, 254);
+		/*
+		 * OVERLAY planes can be below or above the PRIMARY, but cannot
+		 * be above the CURSOR plane.
+		 */
+		unsigned int zpos = primary_zpos + 1 + drm_plane_index(plane);
+
+		drm_plane_create_zpos_property(plane, zpos, 0, 254);
 	} else if (plane->type == DRM_PLANE_TYPE_CURSOR) {
 		drm_plane_create_zpos_immutable_property(plane, 255);
 	}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 42/67] drm/amd/display: Remove register from DCN35 DMCUB diagnostic collection
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (40 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 41/67] drm/amd/display: Move PRIMARY plane zpos higher Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 43/67] drm/amd/display: remove dpp pipes on failure to update pipe params Zaeem Mohamed
                   ` (24 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Nicholas Kazlauskas, Duncan Ma, Zaeem Mohamed

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
These registers should not be read from driver and triggering the
security violation when DMCUB work times out and diagnostics are
collected blocks Z8 entry.

[How]
Remove the register read from DCN35.

Reviewed-by: Duncan Ma <duncan.ma@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index 7f53074f4e48..80da117356c0 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -462,7 +462,7 @@ uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub)
 void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data)
 {
 	uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset;
-	uint32_t is_traceport_enabled, is_cw0_enabled, is_cw6_enabled;
+	uint32_t is_traceport_enabled, is_cw6_enabled;
 
 	if (!dmub || !diag_data)
 		return;
@@ -513,9 +513,6 @@ void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnosti
 	REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled);
 	diag_data->is_traceport_en  = is_traceport_enabled;
 
-	REG_GET(DMCUB_REGION3_CW0_TOP_ADDRESS, DMCUB_REGION3_CW0_ENABLE, &is_cw0_enabled);
-	diag_data->is_cw0_enabled = is_cw0_enabled;
-
 	REG_GET(DMCUB_REGION3_CW6_TOP_ADDRESS, DMCUB_REGION3_CW6_ENABLE, &is_cw6_enabled);
 	diag_data->is_cw6_enabled = is_cw6_enabled;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 43/67] drm/amd/display: remove dpp pipes on failure to update pipe params
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (41 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 42/67] drm/amd/display: Remove register from DCN35 DMCUB diagnostic collection Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 44/67] drm/amd/display: remove ODM combine before bandwidth validation Zaeem Mohamed
                   ` (23 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu, Dillon Varone, Zaeem Mohamed

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
There are cases where update pipe params could fail but dpp pipes are already
added to the state. In this case, we should remove dpp pipes so dc state is
restored back. If it is not restored, dc state is corrupted after calling this
function, so if we call the same interface with the corrupted state again, we
may end up programming pipe topology based on a corrupted dc state.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 6d4d4c95243f..7894d3e52a27 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2789,6 +2789,7 @@ bool resource_append_dpp_pipes_for_plane_composition(
 		struct dc_plane_state *plane_state)
 {
 	bool success;
+
 	if (otg_master_pipe->plane_state == NULL)
 		success = add_plane_to_opp_head_pipes(otg_master_pipe,
 				plane_state, new_ctx);
@@ -2796,10 +2797,15 @@ bool resource_append_dpp_pipes_for_plane_composition(
 		success = acquire_secondary_dpp_pipes_and_add_plane(
 				otg_master_pipe, plane_state, new_ctx,
 				cur_ctx, pool);
-	if (success)
+	if (success) {
 		/* when appending a plane mpc slice count changes from 0 to 1 */
 		success = update_pipe_params_after_mpc_slice_count_change(
 				plane_state, new_ctx, pool);
+		if (!success)
+			resource_remove_dpp_pipes_for_plane_composition(new_ctx,
+					pool, plane_state);
+	}
+
 	return success;
 }
 
@@ -2809,6 +2815,7 @@ void resource_remove_dpp_pipes_for_plane_composition(
 		const struct dc_plane_state *plane_state)
 {
 	int i;
+
 	for (i = pool->pipe_count - 1; i >= 0; i--) {
 		struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 44/67] drm/amd/display: remove ODM combine before bandwidth validation
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (42 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 43/67] drm/amd/display: remove dpp pipes on failure to update pipe params Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 45/67] drm/amd/display: use preferred link settings for dp signal only Zaeem Mohamed
                   ` (22 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu, Dillon Varone, Zaeem Mohamed

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
DML1 validation code doesn't have the ability to remove ODM combine.
It will directly translate currently used ODM combine config into ODM
override. If ODM combine is used in the initial state it will only
validate the timing if ODM is used. This is not correct for dynamic ODM u
se case, as ODM is used as an optimization not a hard requirement.

[how]
Remove ODM combine in the initial state before bandwidth validation so
DML will not translate it into ODM override in the initial bandwidth
validation.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index 194422dd979d..5ef10e2b9443 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -2154,6 +2154,8 @@ bool dcn32_internal_validate_bw(struct dc *dc,
 
 	dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
 
+	for (i = 0; i < context->stream_count; i++)
+		resource_update_pipes_for_stream_with_slice_count(context, dc->current_state, dc->res_pool, context->streams[i], 1);
 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
 
 	if (!pipe_cnt) {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 45/67] drm/amd/display: use preferred link settings for dp signal only
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (43 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 44/67] drm/amd/display: remove ODM combine before bandwidth validation Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 46/67] drm/amd/display: Disable DMCUB timeout for DCN35 Zaeem Mohamed
                   ` (21 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu, Dillon Varone, Zaeem Mohamed

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
We set preferred link settings for virtual signal. However we don't support
virtual signal for UHBR link rate. If preferred is set to UHBR link rate, we
will allow virtual signal with UHBR link rate which causes system crashes.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 .../dc/link/protocols/link_dp_capability.c    | 24 ++++++++-----------
 1 file changed, 10 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 41bdadc585b3..00974c50e11f 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -930,21 +930,17 @@ bool link_decide_link_settings(struct dc_stream_state *stream,
 
 	memset(link_setting, 0, sizeof(*link_setting));
 
-	/* if preferred is specified through AMDDP, use it, if it's enough
-	 * to drive the mode
-	 */
-	if (link->preferred_link_setting.lane_count !=
-			LANE_COUNT_UNKNOWN &&
-			link->preferred_link_setting.link_rate !=
-					LINK_RATE_UNKNOWN) {
+	if (dc_is_dp_signal(stream->signal)  &&
+			link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
+			link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) {
+		/* if preferred is specified through AMDDP, use it, if it's enough
+		 * to drive the mode
+		 */
 		*link_setting = link->preferred_link_setting;
-		return true;
-	}
-
-	/* MST doesn't perform link training for now
-	 * TODO: add MST specific link training routine
-	 */
-	if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+	} else if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+		/* MST doesn't perform link training for now
+		 * TODO: add MST specific link training routine
+		 */
 		decide_mst_link_settings(link, link_setting);
 	} else if (link->connector_signal == SIGNAL_TYPE_EDP) {
 		/* enable edp link optimization for DSC eDP case */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 46/67] drm/amd/display: Disable DMCUB timeout for DCN35
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (44 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 45/67] drm/amd/display: use preferred link settings for dp signal only Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 47/67] drm/amd/display: Check otg_master pointer before use it Zaeem Mohamed
                   ` (20 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Nicholas Kazlauskas, ovidiu.bunea, Zaeem Mohamed

From: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>

[Why]
DMCUB can intermittently take longer than expected to process commands.

Old ASIC policy was to continue while logging a diagnostic error - which
works fine for ASIC without IPS, but with IPS this could lead to a race
condition where we attempt to access DCN state while it's inaccessible,
leading to a system hang when the NIU port is not disabled or register
accesses that timeout and the display configuration in an undefined
state.

[How]
We need to investigate why these accesses take longer than expected, but
for now we should disable the timeout on DCN35 to avoid this race
condition. Since the waits happen only at lower interrupt levels the
risk of taking too long at higher IRQ and causing a system watchdog
timeout are minimal.

Reviewed-by: Ovidiu Bunea <user did not set an email>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
---
 drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 391f9f69a923..5edccd565b05 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -785,6 +785,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 	.ips2_entry_delay_us = 800,
 	.disable_dmub_reallow_idle = false,
 	.static_screen_wait_frames = 2,
+	.disable_timeout = true,
 };
 
 static const struct dc_panel_config panel_config_defaults = {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 47/67] drm/amd/display: Check otg_master pointer before use it
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (45 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 46/67] drm/amd/display: Disable DMCUB timeout for DCN35 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 48/67] drm/amd/display: Minor cleanup for DCN401 cursor related code Zaeem Mohamed
                   ` (19 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Rodrigo Siqueira, Zaeem Mohamed

From: Rodrigo Siqueira <rodrigo.siqueira@amd.com>

Coverity highlighted that the parameter otg_master is referenced before
the if condition that validates it, which means that the code might have
some attempt to access a null pointer. This commit addresses this issue
by moving the pointer verification to the beginning of the function and
initializing all the values right after it.

Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/core/dc_resource.c | 22 +++++++++++++------
 1 file changed, 15 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 7894d3e52a27..e047ea4ff3aa 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2077,15 +2077,23 @@ int resource_get_odm_slice_index(const struct pipe_ctx *pipe_ctx)
 int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,
 		bool is_last_segment)
 {
-	const struct dc_crtc_timing *timing = &otg_master->stream->timing;
-	int count = resource_get_odm_slice_count(otg_master);
-	int h_active = timing->h_addressable +
-			timing->h_border_left +
-			timing->h_border_right;
-	int width = h_active / count;
+	const struct dc_crtc_timing *timing;
+	int count;
+	int h_active;
+	int width;
 	bool two_pixel_alignment_required = false;
 
-	if (otg_master && otg_master->stream_res.tg && otg_master->stream)
+	if (!otg_master || !otg_master->stream)
+		return 0;
+
+	timing = &otg_master->stream->timing;
+	count = resource_get_odm_slice_count(otg_master);
+	h_active = timing->h_addressable +
+		   timing->h_border_left +
+		   timing->h_border_right;
+	width = h_active / count;
+
+	if (otg_master->stream_res.tg && otg_master->stream)
 		two_pixel_alignment_required = otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing);
 
 	if ((width % 2) && two_pixel_alignment_required)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 48/67] drm/amd/display: Minor cleanup for DCN401 cursor related code
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (46 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 47/67] drm/amd/display: Check otg_master pointer before use it Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 49/67] drm/amd/display: Fix incorrect size calculation for loop in dcn401 Zaeem Mohamed
                   ` (18 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Sridevi Arvindekar, ilya.bakoulin, Zaeem Mohamed

From: Sridevi Arvindekar <sarvinde@amd.com>

Move pipe_ctx variables to start of the function and add a helpful comment

Co-authored-by: Sridevi Arvindekar <sarvinde@amd.com>
Reviewed-by: Ilya Bakoulin <user did not set an email>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Sridevi Arvindekar <sarvinde@amd.com>
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c   | 5 +++++
 drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 7 +++++--
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 0d58c9d439c6..d60941495fd3 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -2800,6 +2800,11 @@ void dcn20_reset_back_end_for_pipe(
 	if (i == dc->res_pool->pipe_count)
 		return;
 
+/*
+ * In case of a dangling plane, setting this to NULL unconditionally
+ * causes failures during reset hw ctx where, if stream is NULL,
+ * it is expected that the pipe_ctx pointers to pipes and plane are NULL.
+ */
 	pipe_ctx->stream = NULL;
 	DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 					pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 776ec8963cab..fe0bb6147e36 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1099,6 +1099,8 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 	int prev_odm_offset = 0;
 	int next_odm_width = 0;
 	int next_odm_offset = 0;
+	struct pipe_ctx *next_odm_pipe = NULL;
+	struct pipe_ctx *prev_odm_pipe = NULL;
 
 	int x_pos = pos_cpy.x;
 	int y_pos = pos_cpy.y;
@@ -1110,6 +1112,7 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 		}
 	}
 
+
 	/**
 	 * DCN4 moved cursor composition after Scaler, so in HW it is in
 	 * recout space and for HW Cursor position programming need to
@@ -1157,8 +1160,8 @@ void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx)
 	 * next/prev_odm_offset is to account for scaled modes that have underscan
 	 */
 	if (odm_combine_on) {
-		struct pipe_ctx *next_odm_pipe = pipe_ctx->next_odm_pipe;
-		struct pipe_ctx *prev_odm_pipe = pipe_ctx->prev_odm_pipe;
+		next_odm_pipe = pipe_ctx->next_odm_pipe;
+		prev_odm_pipe = pipe_ctx->prev_odm_pipe;
 
 		while (next_odm_pipe != NULL) {
 			next_odm_width += next_odm_pipe->plane_res.scl_data.recout.width;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 49/67] drm/amd/display: Fix incorrect size calculation for loop in dcn401
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (47 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 48/67] drm/amd/display: Minor cleanup for DCN401 cursor related code Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 50/67] drm/amd/display: Fix uninitialized variables " Zaeem Mohamed
                   ` (17 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alex Hung, Harry Wentland, Zaeem Mohamed

From: Alex Hung <alex.hung@amd.com>

[WHY]
fe_clk_en and be_clk_sel have size of 4 but sizeof(fe_clk_en) has
byte size 16 which is lager than the array size.

[HOW]
Use ARRAY_SIZE for calculating size.

This fixes 2 OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index dac31c4cf2a7..6a467c49b4a4 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -885,7 +885,7 @@ static uint8_t dccg401_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t s
 	/* for DPMST, this backend could be used by multiple front end.
 	only disable the backend if this stream_enc_ins is the last active stream enc connected to this back_end*/
 		uint8_t i;
-		for (i = 0; i != link_enc_inst && i < sizeof(fe_clk_en); i++) {
+		for (i = 0; i != link_enc_inst && i < ARRAY_SIZE(fe_clk_en); i++) {
 			if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst)
 				num_enabled_symclk_fe++;
 		}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 50/67] drm/amd/display: Fix uninitialized variables in dcn401
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (48 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 49/67] drm/amd/display: Fix incorrect size calculation for loop in dcn401 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 51/67] drm/amd/display: Remove useless comparison of unsigned int vs. 0 Zaeem Mohamed
                   ` (16 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alex Hung, Harry Wentland, Zaeem Mohamed

From: Alex Hung <alex.hung@amd.com>

This fixes an UNINIT issue reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index fe0bb6147e36..116411aa0a2b 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -805,7 +805,7 @@ enum dc_status dcn401_enable_stream_timing(
 	unsigned int event_triggers = 0;
 	int opp_cnt = 1;
 	int opp_inst[MAX_PIPES] = {0};
-	struct pipe_ctx *opp_heads[MAX_PIPES];
+	struct pipe_ctx *opp_heads[MAX_PIPES] = {0};
 	bool manual_mode;
 	unsigned int tmds_div = PIXEL_RATE_DIV_NA;
 	unsigned int unused_div = PIXEL_RATE_DIV_NA;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 51/67] drm/amd/display: Remove useless comparison of unsigned int vs. 0
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (49 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 50/67] drm/amd/display: Fix uninitialized variables " Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 52/67] Revert "drm/amd/display: Handle HPD_IRQ for internal link" Zaeem Mohamed
                   ` (15 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alex Hung, Harry Wentland, Zaeem Mohamed

From: Alex Hung <alex.hung@amd.com>

[WHY & HOW]
The comparisons of unsigned int with 0 can have no meanings, i.e.
unsigned int >= 0 (always true) or unsigned int < 0 (always false), and
therefore they are removed.

This fixes 12 NO_EFFECT issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 .../gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c |  8 ++++----
 .../drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c    |  8 ++++----
 drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c    |  6 ++----
 drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c  |  6 +++---
 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c          | 11 ++++-------
 drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c      |  2 +-
 drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c          |  2 +-
 drivers/gpu/drm/amd/display/dc/irq/irq_service.c      |  2 +-
 8 files changed, 20 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index aea4bb46856e..a650a9877097 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -320,16 +320,16 @@ static void rn_dump_clk_registers(struct clk_state_registers_and_bypass *regs_an
 	regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 
 	regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+	if (regs_and_bypass->dppclk_bypass > 4)
 		regs_and_bypass->dppclk_bypass = 0;
 	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+	if (regs_and_bypass->dcfclk_bypass > 4)
 		regs_and_bypass->dcfclk_bypass = 0;
 	regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+	if (regs_and_bypass->dispclk_bypass > 4)
 		regs_and_bypass->dispclk_bypass = 0;
 	regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+	if (regs_and_bypass->dprefclk_bypass > 4)
 		regs_and_bypass->dprefclk_bypass = 0;
 
 	if (log_info->enabled) {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index 191d8b969d19..148a0e4cdea2 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -252,16 +252,16 @@ static void vg_dump_clk_registers(struct clk_state_registers_and_bypass *regs_an
 	regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10;
 
 	regs_and_bypass->dppclk_bypass = internal.CLK1_CLK1_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dppclk_bypass < 0 || regs_and_bypass->dppclk_bypass > 4)
+	if (regs_and_bypass->dppclk_bypass > 4)
 		regs_and_bypass->dppclk_bypass = 0;
 	regs_and_bypass->dcfclk_bypass = internal.CLK1_CLK3_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dcfclk_bypass < 0 || regs_and_bypass->dcfclk_bypass > 4)
+	if (regs_and_bypass->dcfclk_bypass > 4)
 		regs_and_bypass->dcfclk_bypass = 0;
 	regs_and_bypass->dispclk_bypass = internal.CLK1_CLK0_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dispclk_bypass < 0 || regs_and_bypass->dispclk_bypass > 4)
+	if (regs_and_bypass->dispclk_bypass > 4)
 		regs_and_bypass->dispclk_bypass = 0;
 	regs_and_bypass->dprefclk_bypass = internal.CLK1_CLK2_BYPASS_CNTL & 0x0007;
-	if (regs_and_bypass->dprefclk_bypass < 0 || regs_and_bypass->dprefclk_bypass > 4)
+	if (regs_and_bypass->dprefclk_bypass > 4)
 		regs_and_bypass->dprefclk_bypass = 0;
 
 	if (log_info->enabled) {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
index 4cdd4dacb761..f5e1d9caee4c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_mem_input.c
@@ -642,8 +642,7 @@ static void dce_mi_program_surface_config(
 	program_tiling(dce_mi, tiling_info);
 	program_size_and_rotation(dce_mi, rotation, plane_size);
 
-	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 		program_grph_pixel_format(dce_mi, format);
 }
 
@@ -663,8 +662,7 @@ static void dce60_mi_program_surface_config(
 	program_tiling(dce_mi, tiling_info);
 	dce60_program_size(dce_mi, rotation, plane_size);
 
-	if (format >= SURFACE_PIXEL_FORMAT_GRPH_BEGIN &&
-		format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
+	if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 		program_grph_pixel_format(dce_mi, format);
 }
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
index 53bd0ae4bab5..af21c0a27f86 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
@@ -359,7 +359,7 @@ void pg_cntl35_mpcc_pg_control(struct pg_cntl *pg_cntl,
 	if (pg_cntl->ctx->dc->idle_optimizations_allowed)
 		return;
 
-	if (mpcc_inst >= 0 && mpcc_inst < MAX_PIPES)
+	if (mpcc_inst < MAX_PIPES)
 		pg_cntl->pg_pipe_res_enable[PG_MPCC][mpcc_inst] = power_on;
 }
 
@@ -369,7 +369,7 @@ void pg_cntl35_opp_pg_control(struct pg_cntl *pg_cntl,
 	if (pg_cntl->ctx->dc->idle_optimizations_allowed)
 		return;
 
-	if (opp_inst >= 0 && opp_inst < MAX_PIPES)
+	if (opp_inst < MAX_PIPES)
 		pg_cntl->pg_pipe_res_enable[PG_OPP][opp_inst] = power_on;
 }
 
@@ -379,7 +379,7 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,
 	if (pg_cntl->ctx->dc->idle_optimizations_allowed)
 		return;
 
-	if (optc_inst >= 0 && optc_inst < MAX_PIPES)
+	if (optc_inst < MAX_PIPES)
 		pg_cntl->pg_pipe_res_enable[PG_OPTC][optc_inst] = power_on;
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
index 525bc8881950..d9e6e70dc394 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
@@ -170,8 +170,7 @@ static enum gpio_result set_config(
 
 		return GPIO_RESULT_OK;
 	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT:
-		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+		if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
 			REG_UPDATE_3(ddc_setup,
 				DC_I2C_DDC1_ENABLE, 1,
 				DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
@@ -180,8 +179,7 @@ static enum gpio_result set_config(
 		}
 	break;
 	case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT:
-		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+		if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
 			REG_UPDATE_3(ddc_setup,
 				DC_I2C_DDC1_ENABLE, 1,
 				DC_I2C_DDC1_EDID_DETECT_ENABLE, 1,
@@ -190,8 +188,7 @@ static enum gpio_result set_config(
 		}
 	break;
 	case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING:
-		if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) &&
-			(hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) {
+		if (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA) {
 			REG_UPDATE_2(ddc_setup,
 				DC_I2C_DDC1_ENABLE, 0,
 				DC_I2C_DDC1_EDID_DETECT_ENABLE, 0);
@@ -231,7 +228,7 @@ void dal_hw_ddc_init(
 	enum gpio_id id,
 	uint32_t en)
 {
-	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+	if (en > GPIO_DDC_LINE_MAX) {
 		ASSERT_CRITICAL(false);
 		*hw_ddc = NULL;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
index f9e847e6555d..6cd50232c432 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
@@ -106,7 +106,7 @@ void dal_hw_generic_init(
 	enum gpio_id id,
 	uint32_t en)
 {
-	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+	if (en > GPIO_DDC_LINE_MAX) {
 		ASSERT_CRITICAL(false);
 		*hw_generic = NULL;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
index 1489fdfaf0e7..3f13a744d07d 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
@@ -127,7 +127,7 @@ void dal_hw_hpd_init(
 	enum gpio_id id,
 	uint32_t en)
 {
-	if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) {
+	if (en > GPIO_DDC_LINE_MAX) {
 		ASSERT_CRITICAL(false);
 		*hw_hpd = NULL;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
index d100edaedbbb..eca3d7ee7e4e 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/irq_service.c
@@ -76,7 +76,7 @@ static const struct irq_source_info *find_irq_source_info(
 	struct irq_service *irq_service,
 	enum dc_irq_source source)
 {
-	if (source >= DAL_IRQ_SOURCES_NUMBER || source < DC_IRQ_SOURCE_INVALID)
+	if (source >= DAL_IRQ_SOURCES_NUMBER)
 		return NULL;
 
 	return &irq_service->info[source];
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 52/67] Revert "drm/amd/display: Handle HPD_IRQ for internal link"
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (50 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 51/67] drm/amd/display: Remove useless comparison of unsigned int vs. 0 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 53/67] drm/amd/display: Disable IPS when it is not allowed Zaeem Mohamed
                   ` (14 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Sung-huai Wang, Wenjing Liu, Zaeem Mohamed

From: Sung-huai Wang <danny.wang@amd.com>

[How&Why]
This reverts commit a410234a0e13. Due to the it effects Replay resync.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Sung-huai Wang <danny.wang@amd.com>
---
 .../dc/link/protocols/link_dp_irq_handler.c   | 24 +++++++------------
 1 file changed, 9 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 5f087e930cb6..96bf135b6f05 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -387,7 +387,6 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 	union device_service_irq device_service_clear = {0};
 	enum dc_status result;
 	bool status = false;
-	bool allow_active = false;
 
 	if (out_link_loss)
 		*out_link_loss = false;
@@ -442,6 +441,12 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 		return false;
 	}
 
+	if (handle_hpd_irq_psr_sink(link))
+		/* PSR-related error was detected and handled */
+		return true;
+
+	handle_hpd_irq_replay_sink(link);
+
 	/* If PSR-related error handled, Main link may be off,
 	 * so do not handle as a normal sink status change interrupt.
 	 */
@@ -463,8 +468,10 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 	 * If we got sink count changed it means
 	 * Downstream port status changed,
 	 * then DM should call DC to do the detection.
+	 * NOTE: Do not handle link loss on eDP since it is internal link
 	 */
-	if (dp_parse_link_loss_status(
+	if ((link->connector_signal != SIGNAL_TYPE_EDP) &&
+			dp_parse_link_loss_status(
 					link,
 					&hpd_irq_dpcd_data)) {
 		/* Connectivity log: link loss */
@@ -473,11 +480,6 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 					sizeof(hpd_irq_dpcd_data),
 					"Status: ");
 
-		if (link->psr_settings.psr_feature_enabled)
-			edp_set_psr_allow_active(link, &allow_active, true, false, NULL);
-		else if (link->replay_settings.replay_allow_active)
-			edp_set_replay_allow_active(link, &allow_active, true, false, NULL);
-
 		if (defer_handling && has_left_work)
 			*has_left_work = true;
 		else
@@ -490,14 +492,6 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 		dp_trace_link_loss_increment(link);
 	}
 
-	if (*out_link_loss == false) {
-		if (handle_hpd_irq_psr_sink(link))
-			/* PSR-related error was detected and handled */
-			return true;
-
-		handle_hpd_irq_replay_sink(link);
-	}
-
 	if (link->type == dc_connection_sst_branch &&
 		hpd_irq_dpcd_data.bytes.sink_cnt.bits.SINK_COUNT
 			!= link->dpcd_sink_count)
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 53/67] drm/amd/display: Disable IPS when it is not allowed.
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (51 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 52/67] Revert "drm/amd/display: Handle HPD_IRQ for internal link" Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 54/67] drm/amd/display: make ODM segment width of YCbCr422 two pixel aligned Zaeem Mohamed
                   ` (13 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, JinZe.Xu, Nicholas Kazlauskas, Zaeem Mohamed

From: "JinZe.Xu" <jinze.xu@amd.com>

[Why&How]
Add flag to disable IPS when it is not allowed.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: JinZe.Xu <jinze.xu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h          | 1 +
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1008cab97c76..c97d9b9d5c17 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -924,6 +924,7 @@ struct dc_debug_options {
 	bool disable_z9_mpc;
 	unsigned int force_fclk_khz;
 	bool enable_tri_buf;
+	bool ips_disallow_entry;
 	bool dmub_offload_enabled;
 	bool dmcub_emulation;
 	bool disable_idle_power_optimizations;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 12687d400092..3e4abfa6d517 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1506,6 +1506,8 @@ void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_
 	if (!dc_dmub_srv || !dc_dmub_srv->dmub)
 		return;
 
+	allow_idle &= (!dc->debug.ips_disallow_entry);
+
 	if (dc_dmub_srv->idle_allowed == allow_idle)
 		return;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 54/67] drm/amd/display: make ODM segment width of YCbCr422 two pixel aligned
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (52 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 53/67] drm/amd/display: Disable IPS when it is not allowed Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 55/67] drm/amd/display: populate hardware_release hook for dcn401 Zaeem Mohamed
                   ` (12 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Wenjing Liu, Dillon Varone, Zaeem Mohamed

From: Wenjing Liu <wenjing.liu@amd.com>

[why]
In YCbCr422 format hardware shares 1 set of chromas CbCr with 2 sets of
lumas Y. Therefore each ODM segment needs to be two pixel aligned. The
commit adds this missing hardwware requirement into ODM segment width
decision logic.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Wenjing Liu <wenjing.liu@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 15 +++++++++++----
 1 file changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index e047ea4ff3aa..76b849bdd914 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -2089,13 +2089,20 @@ int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master,
 	timing = &otg_master->stream->timing;
 	count = resource_get_odm_slice_count(otg_master);
 	h_active = timing->h_addressable +
-		   timing->h_border_left +
-		   timing->h_border_right;
+			timing->h_border_left +
+			timing->h_border_right;
 	width = h_active / count;
 
 	if (otg_master->stream_res.tg && otg_master->stream)
-		two_pixel_alignment_required = otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing);
-
+		two_pixel_alignment_required =
+				otg_master->stream_res.tg->funcs->is_two_pixels_per_container(timing) ||
+				/*
+				 * 422 is sub-sampled horizontally. 1 set of chromas
+				 * (Cb/Cr) is shared for 2 lumas (i.e 2 Y values).
+				 * Therefore even if 422 is still 1 pixel per container,
+				 * ODM segment width still needs to be 2 pixel aligned.
+				 */
+				timing->pixel_encoding == PIXEL_ENCODING_YCBCR422;
 	if ((width % 2) && two_pixel_alignment_required)
 		width++;
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 55/67] drm/amd/display: populate hardware_release hook for dcn401
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (53 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 54/67] drm/amd/display: make ODM segment width of YCbCr422 two pixel aligned Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 56/67] drm/amd/display: Remove reduntant comparisons by Coverity Zaeem Mohamed
                   ` (11 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alvin Lee, Dillon Varone, Zaeem Mohamed

From: Alvin Lee <alvin.lee2@amd.com>

[Description]
hardare_release() is called when driver is removed. Add the missing hook for DCN401

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
---
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 20 +++++++++++++++++++
 .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h |  2 +-
 .../amd/display/dc/hwss/dcn401/dcn401_init.c  |  2 +-
 3 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 116411aa0a2b..4d0c01e866be 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1674,3 +1674,23 @@ void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx,
 	if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP)
 		hws->funcs.edp_backlight_control(link, true);
 }
+
+void dcn401_hardware_release(struct dc *dc)
+{
+	dc_dmub_srv_fams2_update_config(dc, dc->current_state, false);
+
+	/* If pstate unsupported, or still supported
+	 * by firmware, force it supported by dcn
+	 */
+	if (dc->current_state) {
+		if ((!dc->clk_mgr->clks.p_state_change_support ||
+				dc->current_state->bw_ctx.bw.dcn.fams2_stream_count > 0) &&
+				dc->res_pool->hubbub->funcs->force_pstate_change_control)
+			dc->res_pool->hubbub->funcs->force_pstate_change_control(
+					dc->res_pool->hubbub, true, true);
+
+		dc->current_state->bw_ctx.bw.dcn.clk.p_state_change_support = true;
+		dc->clk_mgr->funcs->update_clocks(dc->clk_mgr, dc->current_state, true);
+	}
+}
+
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
index f91159a6e6d4..bada43d4b2eb 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h
@@ -75,7 +75,7 @@ void dcn401_fams2_global_control_lock(struct dc *dc,
 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable);
 void dcn401_fams2_global_control_lock_fast(union block_sequence_params *params);
 void dcn401_unblank_stream(struct pipe_ctx *pipe_ctx, struct dc_link_settings *link_settings);
-
+void dcn401_hardware_release(struct dc *dc);
 void dcn401_update_odm(struct dc *dc, struct dc_state *context,
 		struct pipe_ctx *otg_master);
 #endif /* __DC_HWSS_DCN401_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 8358ba74405f..dabad7feff03 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -79,7 +79,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = {
 	.does_plane_fit_in_mall = NULL,
 	.set_backlight_level = dcn21_set_backlight_level,
 	.set_abm_immediate_disable = dcn21_set_abm_immediate_disable,
-	.hardware_release = dcn30_hardware_release,
+	.hardware_release = dcn401_hardware_release,
 	.set_pipe = dcn21_set_pipe,
 	.enable_lvds_link_output = dce110_enable_lvds_link_output,
 	.enable_tmds_link_output = dce110_enable_tmds_link_output,
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 56/67] drm/amd/display: Remove reduntant comparisons by Coverity
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (54 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 55/67] drm/amd/display: populate hardware_release hook for dcn401 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 57/67] drm/amd/display: Remove NO_EFFECT self-assignment Zaeem Mohamed
                   ` (10 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Ivan Lipski, Sun peng Li, Zaeem Mohamed

From: Ivan Lipski <ivlipski@amd.com>

[WHY]
Coverity analysis of the Upstream display driver code
(amd-staging-drm-next) flagged these three functions as
containing 'CONSTANT_EXPRESSION_RESULT' errors, i. e. the
conditionals are reduntant since their result is predetermined.

fixpt31_32.c:
The two flagged 'ASSERT' lines redundant since they are always true:
- LONG_MAX equals to the largest 'signed long long' number
- res.value is type 'signed long long',

So, the condition inside the 'ASSERTS's is always

link_dp_training.c:
The flagged conditional statement is always false:
- 'max_requested.FFE_PRESET.settings.level' is 4 bits, so its max
  possible value is 15
- 'DP_FFE_PRESET_MAX_LEVEL' equals to 15.

So, the conditional statement is always false and the wrapped code
never executes.

[HOW]
Removed lines flagged by Coverity analysis.

Reviewed-by: Sun peng Li <sunpeng.li@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Ivan Lipski <ivlipski@amd.com>
---
 drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c        | 4 ----
 .../drm/amd/display/dc/link/protocols/link_dp_training.c  | 8 ++++++--
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
index 1726bdf89bae..506f82cd5cc6 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/fixpt31_32.c
@@ -140,8 +140,6 @@ struct fixed31_32 dc_fixpt_mul(struct fixed31_32 arg1, struct fixed31_32 arg2)
 
 	res.value = arg1_int * arg2_int;
 
-	ASSERT(res.value <= LONG_MAX);
-
 	res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
 
 	tmp = arg1_int * arg2_fra;
@@ -185,8 +183,6 @@ struct fixed31_32 dc_fixpt_sqr(struct fixed31_32 arg)
 
 	res.value = arg_int * arg_int;
 
-	ASSERT(res.value <= LONG_MAX);
-
 	res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART;
 
 	tmp = arg_int * arg_fra;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
index a93dd83cd8c0..5a0f574056d4 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c
@@ -329,8 +329,12 @@ static void maximize_lane_settings(const struct link_training_settings *lt_setti
 
 	if (max_requested.PRE_EMPHASIS > PRE_EMPHASIS_MAX_LEVEL)
 		max_requested.PRE_EMPHASIS = PRE_EMPHASIS_MAX_LEVEL;
-	if (max_requested.FFE_PRESET.settings.level > DP_FFE_PRESET_MAX_LEVEL)
-		max_requested.FFE_PRESET.settings.level = DP_FFE_PRESET_MAX_LEVEL;
+
+	/* Note, we are not checking
+	 * if max_requested.FFE_PRESET.settings.level >  DP_FFE_PRESET_MAX_LEVEL,
+	 * since FFE_PRESET.settings.level is 4 bits and DP_FFE_PRESET_MAX_LEVEL equals 15,
+	 * so FFE_PRESET.settings.level will never be greater than 15.
+	 */
 
 	/* make sure the pre-emphasis matches the voltage swing*/
 	if (max_requested.PRE_EMPHASIS >
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 57/67] drm/amd/display: Remove NO_EFFECT self-assignment
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (55 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 56/67] drm/amd/display: Remove reduntant comparisons by Coverity Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 58/67] drm/amd/display: Explicitly cast v_total to signed in a subtraction Zaeem Mohamed
                   ` (9 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alex Hung, Rodrigo Siqueira, Zaeem Mohamed

From: Alex Hung <alex.hung@amd.com>

[WHAT & HOW]
The self-assignments have no effects and thus are removed.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 .../dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c        | 4 ----
 .../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c    | 4 ----
 2 files changed, 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
index 2b240a30d2ec..eceef0fcb316 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
@@ -8919,10 +8919,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out
 			} // prefetch schedule
 		}
 
-		for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
-			mode_lib->ms.use_one_row_for_frame[k] = mode_lib->ms.use_one_row_for_frame[k];
-		}
-
 		s->mSOCParameters.UrgentLatency = mode_lib->ms.UrgLatency;
 		s->mSOCParameters.ExtraLatency = mode_lib->ms.ExtraLatency;
 		s->mSOCParameters.ExtraLatency_sr = mode_lib->ms.ExtraLatency_sr;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
index 6eb3fec87ec1..cfa4c4475821 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c
@@ -2647,10 +2647,6 @@ bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_ou
 			} // prefetch schedule
 		}
 
-		for (k = 0; k < mode_lib->ms.num_active_planes; ++k) {
-			mode_lib->ms.use_one_row_for_frame[k] = mode_lib->ms.use_one_row_for_frame[k];
-		}
-
 		s->mSOCParameters.UrgentLatency = mode_lib->ms.UrgLatency;
 		s->mSOCParameters.ExtraLatency = mode_lib->ms.ExtraLatency;
 		s->mSOCParameters.ExtraLatency_sr = mode_lib->ms.ExtraLatency_sr;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 58/67] drm/amd/display: Explicitly cast v_total to signed in a subtraction
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (56 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 57/67] drm/amd/display: Remove NO_EFFECT self-assignment Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 59/67] drm/amd/display: Block SubVP if hardware rotation is used in DML2.1 Zaeem Mohamed
                   ` (8 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alex Hung, Harry Wentland, Zaeem Mohamed

From: Alex Hung <alex.hung@amd.com>

[WHY & HOW]
v_total is an uint32_t and subtracting an unsigned to a signed will
result in an unsigned which is always >= 0. As a result, the ternary
conditions are always true and thus has no effect.

This is fixed by casting v_total to signed explicitly. This also
avoids v_total subtraction to overflow.

This fixes 1 NO_EFFECT, 2 DEADCODE and 2 INTEGER_OVERFLOW issues reported
by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index 55e1c19b97f1..9b24f448ce50 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -1006,9 +1006,9 @@ static unsigned int dc_stream_get_max_flickerless_instant_vtotal_delta(struct dc
 	int safe_refresh_v_total = (int)div64_s64((long long)stream->timing.pix_clk_100hz*100, safe_refresh_hz*stream->timing.h_total);
 
 	if (increase)
-		return ((stream->timing.v_total - safe_refresh_v_total) >= 0) ? (stream->timing.v_total - safe_refresh_v_total) : 0;
+		return (((int) stream->timing.v_total - safe_refresh_v_total) >= 0) ? (stream->timing.v_total - safe_refresh_v_total) : 0;
 
-	return ((safe_refresh_v_total - stream->timing.v_total) >= 0) ? (safe_refresh_v_total - stream->timing.v_total) : 0;
+	return ((safe_refresh_v_total - (int) stream->timing.v_total) >= 0) ? (safe_refresh_v_total - stream->timing.v_total) : 0;
 }
 
 /*
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 59/67] drm/amd/display: Block SubVP if hardware rotation is used in DML2.1
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (57 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 58/67] drm/amd/display: Explicitly cast v_total to signed in a subtraction Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 60/67] drm/amd/display: Add null check for phantom pipes in prepare mcache Zaeem Mohamed
                   ` (7 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Dillon Varone, Alvin Lee, Zaeem Mohamed

From: Dillon Varone <dillon.varone@amd.com>

[WHY&HOW]
SubVP is not supported when hardware rotation is in use.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 .../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c   | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
index 2e8c836bc632..7272a04b9d1d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c
@@ -929,7 +929,8 @@ static bool all_timings_support_svp(const struct dml2_pmo_instance *pmo,
 
 			/* check recout height covers entire otg vactive, and single plane */
 			if (num_planes_per_stream[plane_descriptor->stream_index] > 1 ||
-					!plane_descriptor->composition.rect_out_height_spans_vactive) {
+					!plane_descriptor->composition.rect_out_height_spans_vactive ||
+					plane_descriptor->composition.rotation_angle != dml2_rotation_0) {
 				return false;
 			}
 		}
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 60/67] drm/amd/display: Add null check for phantom pipes in prepare mcache
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (58 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 59/67] drm/amd/display: Block SubVP if hardware rotation is used in DML2.1 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 61/67] drm/amd/display: Fix missed targets in FAMS2+HWFQ Zaeem Mohamed
                   ` (6 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Dillon Varone, Alvin Lee, Zaeem Mohamed

From: Dillon Varone <dillon.varone@amd.com>

[WHY&HOW]
Sometimes this function is called with a partially deconstructed phantom
stream toplolgy, and should ignore phantoms with no plane state.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 .../gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c  | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
index c4542c3dded9..b442e1f9f204 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c
@@ -325,7 +325,10 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
 		}
 
 		/* get config for each phantom pipe */
-		if (pln_prog->phantom_plane.valid && dc_phantom_pipes[0]) {
+		if (pln_prog->phantom_plane.valid &&
+				dc_phantom_pipes[0] &&
+				dc_main_pipes[0]->stream &&
+				dc_phantom_pipes[0]->plane_state) {
 			mcache_config = &l->build_mcache_programming_params.mcache_configurations[dml_phantom_prog_idx];
 			memset(mcache_config, 0, sizeof(struct dml2_plane_mcache_configuration_descriptor));
 			mcache_config->plane_descriptor = pln_prog->plane_descriptor;
@@ -368,7 +371,10 @@ void dml21_prepare_mcache_programming(struct dc *in_dc, struct dc_state *context
 		}
 
 		/* get config for each phantom pipe */
-		if (pln_prog->phantom_plane.valid && dc_phantom_pipes[0]) {
+		if (pln_prog->phantom_plane.valid &&
+				dc_phantom_pipes[0] &&
+				dc_main_pipes[0]->stream &&
+				dc_phantom_pipes[0]->plane_state) {
 			for (dc_pipe_index = 0; dc_pipe_index < num_pipes; dc_pipe_index++) {
 				ASSERT(dc_phantom_pipes[dc_pipe_index]);
 				if (l->build_mcache_programming_params.per_plane_pipe_mcache_regs[dml_phantom_prog_idx][dc_pipe_index]) {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 61/67] drm/amd/display: Fix missed targets in FAMS2+HWFQ
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (59 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 60/67] drm/amd/display: Add null check for phantom pipes in prepare mcache Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 62/67] drm/amd/display: Do not override dml2.1 reinit Zaeem Mohamed
                   ` (5 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Dillon Varone, Alvin Lee, Zaeem Mohamed

From: Dillon Varone <dillon.varone@amd.com>

[WHY&HOW]
Add additional delay factor when considering a safe time to flip for HWFQ
to be passed in by the driver.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c    | 1 +
 drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 3e4abfa6d517..6ff87b023081 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -1657,6 +1657,7 @@ void dc_dmub_srv_fams2_update_config(struct dc *dc,
 	global_cmd->config.global.max_allow_delay_us = 100 * 1000; //100ms
 	global_cmd->config.global.lock_wait_time_us = 5000; //5ms
 	global_cmd->config.global.recovery_timeout_us = 5000; //5ms
+	global_cmd->config.global.hwfq_flip_programming_delay_us = 100; //100us
 
 	/* copy static feature configuration */
 	global_cmd->config.global.features.all = dc->debug.fams2_config.all;
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 87f2e4e38f9a..3e8d5f2d7429 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -1836,7 +1836,7 @@ struct dmub_cmd_fams2_global_config {
 	uint32_t num_streams;
 	union dmub_fams2_global_feature_config features;
 	uint32_t recovery_timeout_us;
-	uint8_t pad[3];
+	uint32_t hwfq_flip_programming_delay_us;
 };
 
 union dmub_cmd_fams2_config {
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 62/67] drm/amd/display: Do not override dml2.1 reinit
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (60 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 61/67] drm/amd/display: Fix missed targets in FAMS2+HWFQ Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 63/67] drm/amd/display: Avoid overflow from uint32_t to uint8_t Zaeem Mohamed
                   ` (4 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Dillon Varone, Alvin Lee, Zaeem Mohamed

From: Dillon Varone <dillon.varone@amd.com>

[WHY&HOW]
Reinit should return after completing version 2.1 reinit instead of calling
version 2 reinit after.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index f5c2ab0c0d58..17ea15682d3a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -844,7 +844,8 @@ void dml2_reinit(const struct dc *in_dc,
 	// TODO : Temporarily add DCN_VERSION_3_2 for N-1 validation. Remove DCN_VERSION_3_2 after N-1 validation phase is complete.
         if ((in_dc->debug.using_dml21) && (in_dc->ctx->dce_version == DCN_VERSION_4_01 || in_dc->ctx->dce_version == DCN_VERSION_3_2)) {
                 dml21_reinit(in_dc, dml2, config);
-        }
+        	return;
+	}
 
 	dml2_init(in_dc, config, dml2);
 }
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 63/67] drm/amd/display: Avoid overflow from uint32_t to uint8_t
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (61 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 62/67] drm/amd/display: Do not override dml2.1 reinit Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 64/67] drm/amd/display: Update idle hardmins if uclk or fclk requirement changed Zaeem Mohamed
                   ` (3 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Alex Hung, Rodrigo Siqueira, Zaeem Mohamed

From: Alex Hung <alex.hung@amd.com>

[WHAT & HOW]
dmub_rb_cmd's ramping_boundary has size of uint8_t and it is assigned
0xFFFF. Fix it by changing it to uint8_t with value of 0xFF.

This fixes 2 INTEGER_OVERFLOW issues reported by Coverity.

Reviewed-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c       | 2 +-
 drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
index f4987e96fbf9..0d7e7f3b81a1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
@@ -258,7 +258,7 @@ bool dmub_abm_set_pipe(struct abm *abm,
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = abm->ctx;
-	uint32_t ramping_boundary = 0xFFFF;
+	uint8_t ramping_boundary = 0xFF;
 
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
index 804be977ea47..3de65a9f0e6f 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
@@ -142,7 +142,7 @@ static bool dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,
 {
 	union dmub_rb_cmd cmd;
 	struct dc_context *dc = abm->ctx;
-	uint32_t ramping_boundary = 0xFFFF;
+	uint8_t ramping_boundary = 0xFF;
 
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 64/67] drm/amd/display: Update idle hardmins if uclk or fclk requirement changed
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (62 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 63/67] drm/amd/display: Avoid overflow from uint32_t to uint8_t Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 65/67] drm/amd/display: 3.2.288 Zaeem Mohamed
                   ` (2 subsequent siblings)
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Dillon Varone, Alvin Lee, Zaeem Mohamed

From: Dillon Varone <dillon.varone@amd.com>

[WHY&HOW]
Update the idle hardmin with SMU if either clock changed.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
---
 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 28769deaad37..cd1c30fa783a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -940,7 +940,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 	}
 
 	/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
-	if (update_idle_uclk && is_idle_dpm_enabled) {
+	if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
 		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
 		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 65/67] drm/amd/display: 3.2.288
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (63 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 64/67] drm/amd/display: Update idle hardmins if uclk or fclk requirement changed Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 66/67] drm/amd/display: [FW Promotion] Release 0.0.221.0 Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 67/67] drm/amd/display: Disable PHYSYMCLK RCO Zaeem Mohamed
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Aric Cyr, Zaeem Mohamed

From: Aric Cyr <aric.cyr@amd.com>

* FW Release 0.0.221.0
* Fixed missing targets in FAMS2
* Populate hardware_release hook for dcn401
* Disable DMCUB timeout for DCN35
* Move PRIMARY plane zpos higher
* Introduce overlay cursor mode
* Change dram_clock_latency for dcn35 and dcn351
* DCN401 cursor code update

Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Aric Cyr <aric.cyr@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index c97d9b9d5c17..35ca38ea2efa 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -55,7 +55,7 @@ struct aux_payload;
 struct set_config_cmd_payload;
 struct dmub_notification;
 
-#define DC_VER "3.2.287"
+#define DC_VER "3.2.288"
 
 #define MAX_SURFACES 3
 #define MAX_PLANES 6
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 66/67] drm/amd/display: [FW Promotion] Release 0.0.221.0
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (64 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 65/67] drm/amd/display: 3.2.288 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  2024-06-06 21:56 ` [PATCH 67/67] drm/amd/display: Disable PHYSYMCLK RCO Zaeem Mohamed
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Anthony Koo, Zaeem Mohamed

From: Anthony Koo <anthony.koo@amd.com>

 - Create a general command and fix Replay desync error with general cmd

Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Anthony Koo <anthony.koo@amd.com>
---
 .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h   | 61 ++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 3e8d5f2d7429..b75653faf40e 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -3381,7 +3381,25 @@ enum dmub_cmd_replay_type {
 	 * Set adaptive sync sdp enabled
 	 */
 	DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP = 8,
+	/**
+	 * Set Replay General command.
+	 */
+	DMUB_CMD__REPLAY_SET_GENERAL_CMD = 16,
+};
 
+/**
+ * Replay general command sub-types.
+ */
+enum dmub_cmd_replay_general_subtype {
+	REPLAY_GENERAL_CMD_NOT_SUPPORTED = -1,
+	/**
+	 * TODO: For backward compatible, allow new command only.
+	 * REPLAY_GENERAL_CMD_SET_TIMING_SYNC_SUPPORTED,
+	 * REPLAY_GENERAL_CMD_SET_RESIDENCY_FRAMEUPDATE_TIMER,
+	 * REPLAY_GENERAL_CMD_SET_PSEUDO_VTOTAL,
+	 */
+	REPLAY_GENERAL_CMD_DISABLED_ADAPTIVE_SYNC_SDP,
+	REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
 };
 
 /**
@@ -3597,6 +3615,26 @@ struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data {
 
 	uint8_t pad[2];
 };
+struct dmub_cmd_replay_set_general_cmd_data {
+	/**
+	 * Panel Instance.
+	 * Panel isntance to identify which replay_state to use
+	 * Currently the support is only for 0 or 1
+	 */
+	uint8_t panel_inst;
+	/**
+	 * subtype: replay general cmd sub type
+	 */
+	uint8_t subtype;
+
+	uint8_t pad[2];
+	/**
+	 * config data with param1 and param2
+	 */
+	uint32_t param1;
+
+	uint32_t param2;
+};
 
 /**
  * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
@@ -3714,6 +3752,20 @@ struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp {
 	struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data data;
 };
 
+/**
+ * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
+ */
+struct dmub_rb_cmd_replay_set_general_cmd {
+	/**
+	 * Command header.
+	 */
+	struct dmub_cmd_header header;
+	/**
+	 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
+	 */
+	struct dmub_cmd_replay_set_general_cmd_data data;
+};
+
 /**
  * Data passed from driver to FW in  DMUB_CMD__REPLAY_SET_RESIDENCY_FRAMEUPDATE_TIMER command.
  */
@@ -3773,7 +3825,10 @@ union dmub_replay_cmd_set {
 	 * Definition of DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command data.
 	 */
 	struct dmub_cmd_replay_disabled_adaptive_sync_sdp_data disabled_adaptive_sync_sdp_data;
-
+	/**
+	 * Definition of DMUB_CMD__REPLAY_SET_GENERAL_CMD command data.
+	 */
+	struct dmub_cmd_replay_set_general_cmd_data set_general_cmd_data;
 };
 
 /**
@@ -5273,6 +5328,10 @@ union dmub_rb_cmd {
 	 * Definition of a DMUB_CMD__REPLAY_DISABLED_ADAPTIVE_SYNC_SDP command.
 	 */
 	struct dmub_rb_cmd_replay_disabled_adaptive_sync_sdp replay_disabled_adaptive_sync_sdp;
+	/**
+	 * Definition of a DMUB_CMD__REPLAY_SET_GENERAL_CMD command.
+	 */
+	struct dmub_rb_cmd_replay_set_general_cmd replay_set_general_cmd;
 	/**
 	 * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command.
 	 */
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

* [PATCH 67/67] drm/amd/display: Disable PHYSYMCLK RCO
  2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
                   ` (65 preceding siblings ...)
  2024-06-06 21:56 ` [PATCH 66/67] drm/amd/display: [FW Promotion] Release 0.0.221.0 Zaeem Mohamed
@ 2024-06-06 21:56 ` Zaeem Mohamed
  66 siblings, 0 replies; 68+ messages in thread
From: Zaeem Mohamed @ 2024-06-06 21:56 UTC (permalink / raw)
  To: amd-gfx
  Cc: Harry.Wentland, Sunpeng.Li, Rodrigo.Siqueira, Aurabindo.Pillai,
	roman.li, wayne.lin, agustin.gutierrez, chiahsuan.chung,
	jerry.zuo, Daniel Miess, Nicholas Kazlauskas, Zaeem Mohamed

From: Daniel Miess <daniel.miess@amd.com>

[Why]
PHYSYMCLK RCO has been found to lead to crashes in some
corner cases

[How]
Disable PHYSYMCLK RCO debug bit

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
---
 drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c  | 2 +-
 .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c    | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 5edccd565b05..0094ef223c5d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -758,7 +758,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 			.symclk32_se = true,
 			.symclk32_le = true,
 			.symclk_fe = true,
-			.physymclk = true,
+			.physymclk = false,
 			.dpiasymclk = true,
 		}
 	},
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 203fd4aaf9f9..30b40ba0c324 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -738,7 +738,7 @@ static const struct dc_debug_options debug_defaults_drv = {
 			.symclk32_se = true,
 			.symclk32_le = true,
 			.symclk_fe = true,
-			.physymclk = true,
+			.physymclk = false,
 			.dpiasymclk = true,
 		}
 	},
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 68+ messages in thread

end of thread, other threads:[~2024-06-06 21:59 UTC | newest]

Thread overview: 68+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-06-06 21:55 [PATCH 00/67] DC Patches June 3, 2024 Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 01/67] drm/amd/display: Use TPS3 for ALPM on Specific Panel Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 02/67] drm/amd/display: Replay low hz Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 03/67] drm/amd/display: Expand supported Replay residency mode Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 04/67] drm/amd/display: Replay + IPS + ABM in Full Screen VPB Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 05/67] drm/amd/display: Fix Replay Desync Error Test Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 06/67] drm/amd/display: use even ODM slice width for two pixels per container Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 07/67] drm/amd/display: add odm_slice_rect parameter in spl_in Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 08/67] drm/amd/display: Remove redundant if conditions Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 09/67] drm/amd/display: Remove unreachable check Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 10/67] drm/amd/display: Remove redundant ternary operation Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 11/67] drm/amd/display: Remove dcn32_smu13 duplicate header Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 12/67] drm/amd/display: Remove NULL assignment for stream_status Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 13/67] drm/amd/display: Change AVI Info Frame version to 4 for OVT Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 14/67] drm/amd/display: Return after Init Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 15/67] drm/amd/display: Fix multiple cursors when using 4 displays on a contiguous large surface Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 16/67] drm/amd/display: reduce ODM slice count to initial new dc state only when needed Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 17/67] drm/amd/display: Update FIXED_VS retimer training pattern delay Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 18/67] drm/amd/display: Add fallback defaults for invalid LTTPR DPCD caps Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 19/67] drm/amd/display: Ignore phantom DTBCLK requirement Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 20/67] drm/amd/display: Add sequential ONO sequencing for DCN35 Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 21/67] drm/amd/display: [FW Promotion] Release 0.0.220.0 Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 22/67] drm/amd/display: added NULL check at start of dc_validate_stream Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 23/67] drm/amd/display: Add config support entry to replay caps debugfs Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 24/67] drm/amd/display: Ignore UHBR13.5 cable ID cap for passive cable max link rate Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 25/67] drm/amd/display: Remove duplicate 'update_idle_uclk' in dcn401 clk_mgr code Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 26/67] drm/amd/display: Use the SPDX license identifier for dmub_replay files Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 27/67] drm/amd/display: DCN401 cusor code update Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 28/67] drm/amd/display: Prevent overflow on DTO calculation Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 29/67] drm/amd/display: Disable boot optimization for DCN401 Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 30/67] drm/amd/display: Update efficiency bandwidth for dcn351 Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 31/67] drm/amd/display: Avoid programming DTO if Refclk is 0 Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 32/67] drm/amd/display: Adjust debug msg for usb4/tbt Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 33/67] drm/amd/display: Defer the setting of link hpd status " Zaeem Mohamed
2024-06-06 21:55 ` [PATCH 34/67] drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAX Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 35/67] drm/amd/display: Change dram_clock_latency to 34us for dcn351 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 36/67] drm/amd/display: change dram_clock_latency to 34us for dcn35 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 37/67] drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_compute Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 38/67] drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode() Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 39/67] drm/amd/display: define abm debug interface Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 40/67] drm/amd/display: Introduce overlay cursor mode Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 41/67] drm/amd/display: Move PRIMARY plane zpos higher Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 42/67] drm/amd/display: Remove register from DCN35 DMCUB diagnostic collection Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 43/67] drm/amd/display: remove dpp pipes on failure to update pipe params Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 44/67] drm/amd/display: remove ODM combine before bandwidth validation Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 45/67] drm/amd/display: use preferred link settings for dp signal only Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 46/67] drm/amd/display: Disable DMCUB timeout for DCN35 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 47/67] drm/amd/display: Check otg_master pointer before use it Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 48/67] drm/amd/display: Minor cleanup for DCN401 cursor related code Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 49/67] drm/amd/display: Fix incorrect size calculation for loop in dcn401 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 50/67] drm/amd/display: Fix uninitialized variables " Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 51/67] drm/amd/display: Remove useless comparison of unsigned int vs. 0 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 52/67] Revert "drm/amd/display: Handle HPD_IRQ for internal link" Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 53/67] drm/amd/display: Disable IPS when it is not allowed Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 54/67] drm/amd/display: make ODM segment width of YCbCr422 two pixel aligned Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 55/67] drm/amd/display: populate hardware_release hook for dcn401 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 56/67] drm/amd/display: Remove reduntant comparisons by Coverity Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 57/67] drm/amd/display: Remove NO_EFFECT self-assignment Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 58/67] drm/amd/display: Explicitly cast v_total to signed in a subtraction Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 59/67] drm/amd/display: Block SubVP if hardware rotation is used in DML2.1 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 60/67] drm/amd/display: Add null check for phantom pipes in prepare mcache Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 61/67] drm/amd/display: Fix missed targets in FAMS2+HWFQ Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 62/67] drm/amd/display: Do not override dml2.1 reinit Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 63/67] drm/amd/display: Avoid overflow from uint32_t to uint8_t Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 64/67] drm/amd/display: Update idle hardmins if uclk or fclk requirement changed Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 65/67] drm/amd/display: 3.2.288 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 66/67] drm/amd/display: [FW Promotion] Release 0.0.221.0 Zaeem Mohamed
2024-06-06 21:56 ` [PATCH 67/67] drm/amd/display: Disable PHYSYMCLK RCO Zaeem Mohamed

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