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From: Luben Tuikov <luben.tuikov@amd.com>
To: Andrey Grodzovsky <andrey.grodzovsky@amd.com>,
	amd-gfx@lists.freedesktop.org
Cc: alexdeucher@gmail.com, ckoenig.leichtzumerken@gmail.com,
	Marek.Olsak@amd.com, Ken.Qiao@amd.com
Subject: Re: [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync
Date: Thu, 26 Mar 2020 19:17:53 -0400
Message-ID: <56039ad5-32f0-6c70-992f-07e7cad7a4af@amd.com> (raw)
In-Reply-To: <1585252968-1218-5-git-send-email-andrey.grodzovsky@amd.com>

On 2020-03-26 16:02, Andrey Grodzovsky wrote:
> This flag used to avoid calling mem_sync without need.

The title of this patch means that the flag is an "enabler" flag,
i.e. when present, it enables something to happen (flush caches).

While the description text in the commit implies that the flag is
a "disabler" flag--i.e. when present, it, quote "avoids"
mem sync, "without need".

I'd much rather the commit text simply expound on the title
of the commit, something like:

"When this flag is set in the CS IB flags, it causes
a memory cache flush of the GFX." or something to that effect.

With that fixed, series is Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>

Regards,
Luben

> 
> v2:
> Move new flag to drm_amdgpu_cs_chunk_ib.flags
> Bump up UAPI version
> Remove condition on job != null to emit mem_sync
> 
> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c  | 3 +++
>  include/uapi/drm/amdgpu_drm.h           | 4 ++++
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> index 28bb840..f18d974 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
> @@ -85,9 +85,10 @@
>   * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches
>   * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask
>   * - 3.36.0 - Allow reading more status registers on si/cik
> + * - 3.37.0 - Add AMDGPU_IB_FLAG_EMIT_MEM_SYNC
>   */
>  #define KMS_DRIVER_MAJOR	3
> -#define KMS_DRIVER_MINOR	36
> +#define KMS_DRIVER_MINOR	37
>  #define KMS_DRIVER_PATCHLEVEL	0
>  
>  int amdgpu_vram_limit = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> index bece01f..a8aa787 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
> @@ -182,6 +182,9 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
>  		dma_fence_put(tmp);
>  	}
>  
> +	if ((ib->flags & AMDGPU_IB_FLAG_EMIT_MEM_SYNC) && ring->funcs->emit_mem_sync)
> +		ring->funcs->emit_mem_sync(ring);
> +
>  	if (ring->funcs->insert_start)
>  		ring->funcs->insert_start(ring);
>  
> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h
> index cfbec27..5f7a4f5 100644
> --- a/include/uapi/drm/amdgpu_drm.h
> +++ b/include/uapi/drm/amdgpu_drm.h
> @@ -601,6 +601,10 @@ union drm_amdgpu_cs {
>   */
>  #define AMDGPU_IB_FLAGS_SECURE  (1 << 5)
>  
> +/* Tell KMD to flush and invalidate caches
> + */
> +#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC  (1 << 6)
> +
>  struct drm_amdgpu_cs_chunk_ib {
>  	__u32 _pad;
>  	/** AMDGPU_IB_FLAG_* */
> 

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  reply index

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-26 20:02 [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Andrey Grodzovsky
2020-03-26 20:02 ` [PATCH v2 1/4] drm/amdgpu: Add new ring callback to insert memory sync Andrey Grodzovsky
2020-03-26 20:02 ` [PATCH v2 2/4] drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion Andrey Grodzovsky
2020-03-26 23:09   ` Luben Tuikov
2020-03-26 20:02 ` [PATCH v2 3/4] drm/amdgpu: Add mem_sync implementation for all the ASICs Andrey Grodzovsky
2020-03-26 20:02 ` [PATCH v2 4/4] drm/amdgpu: Add a UAPI flag for user to call mem_sync Andrey Grodzovsky
2020-03-26 23:17   ` Luben Tuikov [this message]
2020-03-26 23:20 ` [PATCH v2 0/4] Invalidate and flush caches at the beginning of every gfx IB Luben Tuikov

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