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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only] Fixed locally. Alex ________________________________ From: Lazar, Lijo Sent: Wednesday, September 22, 2021 3:37 AM To: Deucher, Alexander ; amd-gfx@lists.freedeskt= op.org Subject: Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP version che= cking On 9/21/2021 11:36 PM, Alex Deucher wrote: > Use IP versions rather than asic_type to differentiate > IP version specific features. > > Signed-off-by: Alex Deucher > --- > .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++++++++++-------- > 1 file changed, 109 insertions(+), 85 deletions(-) > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/= gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 07adac1a8c42..e189d72f08e9 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -1342,16 +1342,23 @@ static int amdgpu_dm_init(struct amdgpu_device *a= dev) > case CHIP_CARRIZO: > case CHIP_STONEY: > case CHIP_RAVEN: > - case CHIP_RENOIR: > - init_data.flags.gpu_vm_support =3D true; > - if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) > - init_data.flags.disable_dmcu =3D true; > - break; > - case CHIP_VANGOGH: > - case CHIP_YELLOW_CARP: > init_data.flags.gpu_vm_support =3D true; > break; > default: > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(2, 1, 0): > + init_data.flags.gpu_vm_support =3D true; > + if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)= ) > + init_data.flags.disable_dmcu =3D true; > + break; > + case IP_VERSION(3, 0, 1): > + case IP_VERSION(3, 1, 2): > + case IP_VERSION(3, 1, 3): > + init_data.flags.gpu_vm_support =3D true; > + break; > + default: > + break; > + } > break; > } > > @@ -1442,7 +1449,7 @@ static int amdgpu_dm_init(struct amdgpu_device *ade= v) > #endif > > #ifdef CONFIG_DRM_AMD_DC_HDCP > - if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >=3D CHIP_RA= VEN) { > + if (adev->dm.dc->caps.max_links > 0 && adev->family >=3D AMDGPU_FAM= ILY_RV) { > adev->dm.hdcp_workqueue =3D hdcp_create_workqueue(adev, &i= nit_params.cp_psp, adev->dm.dc); > > if (!adev->dm.hdcp_workqueue) > @@ -1637,15 +1644,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev= ) > case CHIP_VEGA10: > case CHIP_VEGA12: > case CHIP_VEGA20: > - case CHIP_NAVI10: > - case CHIP_NAVI14: > - case CHIP_RENOIR: > - case CHIP_SIENNA_CICHLID: > - case CHIP_NAVY_FLOUNDER: > - case CHIP_DIMGREY_CAVEFISH: > - case CHIP_BEIGE_GOBY: > - case CHIP_VANGOGH: > - case CHIP_YELLOW_CARP: > return 0; > case CHIP_NAVI12: > fw_name_dmcu =3D FIRMWARE_NAVI12_DMCU; > @@ -1659,6 +1657,20 @@ static int load_dmcu_fw(struct amdgpu_device *adev= ) > return 0; > break; > default: > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(2, 0, 2): > + case IP_VERSION(2, 0, 0): > + case IP_VERSION(2, 1, 0): > + case IP_VERSION(3, 0, 0): > + case IP_VERSION(3, 0, 2): > + case IP_VERSION(3, 0, 3): > + case IP_VERSION(3, 0, 1): > + case IP_VERSION(3, 1, 2): > + case IP_VERSION(3, 1, 3): > + return 0; > + default: > + break; > + } > DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type= ); > return -EINVAL; > } > @@ -1737,34 +1749,36 @@ static int dm_dmub_sw_init(struct amdgpu_device *= adev) > enum dmub_status status; > int r; > > - switch (adev->asic_type) { > - case CHIP_RENOIR: > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(2, 1, 0): > dmub_asic =3D DMUB_ASIC_DCN21; > fw_name_dmub =3D FIRMWARE_RENOIR_DMUB; > if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id)) > fw_name_dmub =3D FIRMWARE_GREEN_SARDINE_DMUB; > break; > - case CHIP_SIENNA_CICHLID: > - dmub_asic =3D DMUB_ASIC_DCN30; > - fw_name_dmub =3D FIRMWARE_SIENNA_CICHLID_DMUB; > - break; > - case CHIP_NAVY_FLOUNDER: > - dmub_asic =3D DMUB_ASIC_DCN30; > - fw_name_dmub =3D FIRMWARE_NAVY_FLOUNDER_DMUB; > + case IP_VERSION(3, 0, 0): > + if (adev->ip_versions[GC_HWIP] =3D=3D IP_VERSION(10, 3, 0))= { > + dmub_asic =3D DMUB_ASIC_DCN30; > + fw_name_dmub =3D FIRMWARE_SIENNA_CICHLID_DMUB; > + } else { > + dmub_asic =3D DMUB_ASIC_DCN30; > + fw_name_dmub =3D FIRMWARE_NAVY_FLOUNDER_DMUB; > + } > break; > - case CHIP_VANGOGH: > + case IP_VERSION(3, 0, 1): > dmub_asic =3D DMUB_ASIC_DCN301; > fw_name_dmub =3D FIRMWARE_VANGOGH_DMUB; > break; > - case CHIP_DIMGREY_CAVEFISH: > + case IP_VERSION(3, 0, 2): > dmub_asic =3D DMUB_ASIC_DCN302; > fw_name_dmub =3D FIRMWARE_DIMGREY_CAVEFISH_DMUB; > break; > - case CHIP_BEIGE_GOBY: > + case IP_VERSION(3, 0, 3): > dmub_asic =3D DMUB_ASIC_DCN303; > fw_name_dmub =3D FIRMWARE_BEIGE_GOBY_DMUB; > break; > - case CHIP_YELLOW_CARP: > + case IP_VERSION(3, 1, 2): > + case IP_VERSION(3, 1, 3): > dmub_asic =3D DMUB_ASIC_DCN31; > fw_name_dmub =3D FIRMWARE_YELLOW_CARP_DMUB; > break; > @@ -2063,10 +2077,9 @@ static int amdgpu_dm_smu_write_watermarks_table(st= ruct amdgpu_device *adev) > * therefore, this function apply to navi10/12/14 but not Renoir > * * > */ > - switch(adev->asic_type) { > - case CHIP_NAVI10: > - case CHIP_NAVI14: > - case CHIP_NAVI12: > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(2, 0, 2): > + case IP_VERSION(2, 0, 0): > break; > default: > return 0; > @@ -3287,7 +3300,7 @@ static int dce110_register_irq_handlers(struct amdg= pu_device *adev) > int i; > unsigned client_id =3D AMDGPU_IRQ_CLIENTID_LEGACY; > > - if (adev->asic_type >=3D CHIP_VEGA10) > + if (adev->family >=3D AMDGPU_FAMILY_AI) > client_id =3D SOC15_IH_CLIENTID_DCE; > > int_params.requested_polarity =3D INTERRUPT_POLARITY_DEFAULT; > @@ -4072,18 +4085,19 @@ static int amdgpu_dm_initialize_drm_device(struct= amdgpu_device *adev) > > #if defined(CONFIG_DRM_AMD_DC_DCN) > /* Use Outbox interrupt */ > - switch (adev->asic_type) { > - case CHIP_SIENNA_CICHLID: > - case CHIP_NAVY_FLOUNDER: > - case CHIP_YELLOW_CARP: > - case CHIP_RENOIR: > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(3, 0, 0): > + case IP_VERSION(3, 1, 2): > + case IP_VERSION(3, 1, 3): > + case IP_VERSION(2, 1, 0): > if (register_outbox_irq_handlers(dm->adev)) { > DRM_ERROR("DM: Failed to initialize IRQ\n"); > goto fail; > } > break; > default: > - DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", a= dev->asic_type); > + DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\= n", > + adev->ip_versions[DCE_HWIP]); > } > #endif > > @@ -4171,16 +4185,6 @@ static int amdgpu_dm_initialize_drm_device(struct = amdgpu_device *adev) > break; > #if defined(CONFIG_DRM_AMD_DC_DCN) > case CHIP_RAVEN: > - case CHIP_NAVI12: > - case CHIP_NAVI10: > - case CHIP_NAVI14: > - case CHIP_RENOIR: > - case CHIP_SIENNA_CICHLID: > - case CHIP_NAVY_FLOUNDER: > - case CHIP_DIMGREY_CAVEFISH: > - case CHIP_BEIGE_GOBY: > - case CHIP_VANGOGH: > - case CHIP_YELLOW_CARP: > if (dcn10_register_irq_handlers(dm->adev)) { > DRM_ERROR("DM: Failed to initialize IRQ\n"); > goto fail; > @@ -4188,6 +4192,26 @@ static int amdgpu_dm_initialize_drm_device(struct = amdgpu_device *adev) > break; > #endif > default: > +#if defined(CONFIG_DRM_AMD_DC_DCN) > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(2, 0, 2): > + case IP_VERSION(2, 0, 0): > + case IP_VERSION(2, 1, 0): > + case IP_VERSION(3, 0, 0): > + case IP_VERSION(3, 0, 2): > + case IP_VERSION(3, 0, 3): > + case IP_VERSION(3, 0, 1): > + case IP_VERSION(3, 1, 2): > + case IP_VERSION(3, 1, 3): > + if (dcn10_register_irq_handlers(dm->adev)) { > + DRM_ERROR("DM: Failed to initialize IRQ\n")= ; > + goto fail; > + } > + break; > + default: > + break; > + } > +#endif > DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type= ); > goto fail; > } > @@ -4338,38 +4362,43 @@ static int dm_early_init(void *handle) > break; > #if defined(CONFIG_DRM_AMD_DC_DCN) > case CHIP_RAVEN: > - case CHIP_RENOIR: > - case CHIP_VANGOGH: > - adev->mode_info.num_crtc =3D 4; > - adev->mode_info.num_hpd =3D 4; > - adev->mode_info.num_dig =3D 4; > - break; > - case CHIP_NAVI10: > - case CHIP_NAVI12: > - case CHIP_SIENNA_CICHLID: > - case CHIP_NAVY_FLOUNDER: > - adev->mode_info.num_crtc =3D 6; > - adev->mode_info.num_hpd =3D 6; > - adev->mode_info.num_dig =3D 6; > - break; > - case CHIP_YELLOW_CARP: > adev->mode_info.num_crtc =3D 4; > adev->mode_info.num_hpd =3D 4; > adev->mode_info.num_dig =3D 4; > break; > - case CHIP_NAVI14: > - case CHIP_DIMGREY_CAVEFISH: > - adev->mode_info.num_crtc =3D 5; > - adev->mode_info.num_hpd =3D 5; > - adev->mode_info.num_dig =3D 5; > - break; > - case CHIP_BEIGE_GOBY: > - adev->mode_info.num_crtc =3D 2; > - adev->mode_info.num_hpd =3D 2; > - adev->mode_info.num_dig =3D 2; > - break; > #endif > default: > +#if defined(CONFIG_DRM_AMD_DC_DCN) > + switch (adev->ip_versions[DCE_HWIP]) { > + case IP_VERSION(2, 0, 2): > + case IP_VERSION(3, 0, 0): > + adev->mode_info.num_crtc =3D 6; > + adev->mode_info.num_hpd =3D 6; > + adev->mode_info.num_dig =3D 6; > + break; > + case IP_VERSION(2, 0, 0): > + case IP_VERSION(3, 0, 2): > + adev->mode_info.num_crtc =3D 5; > + adev->mode_info.num_hpd =3D 5; > + adev->mode_info.num_dig =3D 5; > + break; > + case IP_VERSION(3, 0, 3): > + adev->mode_info.num_crtc =3D 2; > + adev->mode_info.num_hpd =3D 2; > + adev->mode_info.num_dig =3D 2; > + break; > + case IP_VERSION(3, 0, 1): > + case IP_VERSION(2, 1, 0): > + case IP_VERSION(3, 1, 2): > + case IP_VERSION(3, 1, 3): > + adev->mode_info.num_crtc =3D 4; > + adev->mode_info.num_hpd =3D 4; > + adev->mode_info.num_dig =3D 4; > + break; > + default: > + break; > + } > +#endif > DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type= ); > return -EINVAL; > } > @@ -4590,12 +4619,7 @@ fill_gfx9_tiling_info_from_device(const struct amd= gpu_device *adev, > tiling_info->gfx9.num_rb_per_se =3D > adev->gfx.config.gb_addr_config_fields.num_rb_per_se; > tiling_info->gfx9.shaderEnable =3D 1; > - if (adev->asic_type =3D=3D CHIP_SIENNA_CICHLID || > - adev->asic_type =3D=3D CHIP_NAVY_FLOUNDER || > - adev->asic_type =3D=3D CHIP_DIMGREY_CAVEFISH || > - adev->asic_type =3D=3D CHIP_BEIGE_GOBY || > - adev->asic_type =3D=3D CHIP_YELLOW_CARP || > - adev->asic_type =3D=3D CHIP_VANGOGH) > + if (adev->ip_versions[GC_HWIP] >=3D IP_VERSION(10, 3, 0)) > tiling_info->gfx9.num_pkrs =3D adev->gfx.config.gb_addr_co= nfig_fields.num_pkrs; > } > > @@ -5036,7 +5060,7 @@ get_plane_modifiers(const struct amdgpu_device *ade= v, unsigned int plane_type, u > case AMDGPU_FAMILY_NV: > case AMDGPU_FAMILY_VGH: > case AMDGPU_FAMILY_YC: > - if (adev->asic_type >=3D CHIP_SIENNA_CICHLID) > + if (adev->ip_versions[GC_HWIP] >=3D IP_VERSION(10, 3, 0)) > add_gfx10_3_modifiers(adev, mods, &size, &capacity= ); > else > add_gfx10_1_modifiers(adev, mods, &size, &capacity= ); > @@ -7647,7 +7671,7 @@ static int amdgpu_dm_plane_init(struct amdgpu_displ= ay_manager *dm, > DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | > DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; > > - if (dm->adev->asic_type >=3D CHIP_BONAIRE && > + if (dm->adev->family >=3D AMDGPU_FAMILY_CI && This doesn't look related. Thanks, Lijo > plane->type !=3D DRM_PLANE_TYPE_CURSOR) > drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_= 0, > supported_rotations); > --_000_BL1PR12MB5144515BAD46970444CE2749F7A29BL1PR12MB5144namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only]


Fixed locally.

Alex

From: Lazar, Lijo <Lijo.= Lazar@amd.com>
Sent: Wednesday, September 22, 2021 3:37 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@li= sts.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 29/66] drm/amdgpu/display/dm: convert to IP vers= ion checking
 


On 9/21/2021 11:36 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 194 ++++++= ++++--------
>   1 file changed, 109 insertions(+), 85 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> index 07adac1a8c42..e189d72f08e9 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
> @@ -1342,16 +1342,23 @@ static int amdgpu_dm_init(struct amdgpu_device= *adev)
>        case CHIP_CARRIZO:
>        case CHIP_STONEY:
>        case CHIP_RAVEN:
> -     case CHIP_RENOIR:
> -           &nb= sp; init_data.flags.gpu_vm_support =3D true;
> -           &nb= sp; if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
> -           &nb= sp;         init_data.flags.disable= _dmcu =3D true;
> -           &nb= sp; break;
> -     case CHIP_VANGOGH:
> -     case CHIP_YELLOW_CARP:
>            = ;    init_data.flags.gpu_vm_support =3D true;
>            = ;    break;
>        default:
> +           &nb= sp; switch (adev->ip_versions[DCE_HWIP]) {
> +           &nb= sp; case IP_VERSION(2, 1, 0):
> +           &nb= sp;         init_data.flags.gpu_vm_= support =3D true;
> +           &nb= sp;         if (ASICREV_IS_GREEN_SA= RDINE(adev->external_rev_id))
> +           &nb= sp;            =      init_data.flags.disable_dmcu =3D true;
> +           &nb= sp;         break;
> +           &nb= sp; case IP_VERSION(3, 0, 1):
> +           &nb= sp; case IP_VERSION(3, 1, 2):
> +           &nb= sp; case IP_VERSION(3, 1, 3):
> +           &nb= sp;         init_data.flags.gpu_vm_= support =3D true;
> +           &nb= sp;         break;
> +           &nb= sp; default:
> +           &nb= sp;         break;
> +           &nb= sp; }
>            = ;    break;
>        }
>  
> @@ -1442,7 +1449,7 @@ static int amdgpu_dm_init(struct amdgpu_device *= adev)
>   #endif
>  
>   #ifdef CONFIG_DRM_AMD_DC_HDCP
> -     if (adev->dm.dc->caps.max_links > 0= && adev->asic_type >=3D CHIP_RAVEN) {
> +     if (adev->dm.dc->caps.max_links > 0= && adev->family >=3D AMDGPU_FAMILY_RV) {
>            = ;    adev->dm.hdcp_workqueue =3D hdcp_create_workqueue(ad= ev, &init_params.cp_psp, adev->dm.dc);
>  
>            = ;    if (!adev->dm.hdcp_workqueue)
> @@ -1637,15 +1644,6 @@ static int load_dmcu_fw(struct amdgpu_device *a= dev)
>        case CHIP_VEGA10:
>        case CHIP_VEGA12:
>        case CHIP_VEGA20:
> -     case CHIP_NAVI10:
> -     case CHIP_NAVI14:
> -     case CHIP_RENOIR:
> -     case CHIP_SIENNA_CICHLID:
> -     case CHIP_NAVY_FLOUNDER:
> -     case CHIP_DIMGREY_CAVEFISH:
> -     case CHIP_BEIGE_GOBY:
> -     case CHIP_VANGOGH:
> -     case CHIP_YELLOW_CARP:
>            = ;    return 0;
>        case CHIP_NAVI12:
>            = ;    fw_name_dmcu =3D FIRMWARE_NAVI12_DMCU;
> @@ -1659,6 +1657,20 @@ static int load_dmcu_fw(struct amdgpu_device *a= dev)
>            = ;            return = 0;
>            = ;    break;
>        default:
> +           &nb= sp; switch (adev->ip_versions[DCE_HWIP]) {
> +           &nb= sp; case IP_VERSION(2, 0, 2):
> +           &nb= sp; case IP_VERSION(2, 0, 0):
> +           &nb= sp; case IP_VERSION(2, 1, 0):
> +           &nb= sp; case IP_VERSION(3, 0, 0):
> +           &nb= sp; case IP_VERSION(3, 0, 2):
> +           &nb= sp; case IP_VERSION(3, 0, 3):
> +           &nb= sp; case IP_VERSION(3, 0, 1):
> +           &nb= sp; case IP_VERSION(3, 1, 2):
> +           &nb= sp; case IP_VERSION(3, 1, 3):
> +           &nb= sp;         return 0;
> +           &nb= sp; default:
> +           &nb= sp;         break;
> +           &nb= sp; }
>            = ;    DRM_ERROR("Unsupported ASIC type: 0x%X\n", ad= ev->asic_type);
>            = ;    return -EINVAL;
>        }
> @@ -1737,34 +1749,36 @@ static int dm_dmub_sw_init(struct amdgpu_devic= e *adev)
>        enum dmub_status status;
>        int r;
>  
> -     switch (adev->asic_type) {
> -     case CHIP_RENOIR:
> +     switch (adev->ip_versions[DCE_HWIP]) { > +     case IP_VERSION(2, 1, 0):
>            = ;    dmub_asic =3D DMUB_ASIC_DCN21;
>            = ;    fw_name_dmub =3D FIRMWARE_RENOIR_DMUB;
>            = ;    if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))=
>            = ;            fw_name= _dmub =3D FIRMWARE_GREEN_SARDINE_DMUB;
>            = ;    break;
> -     case CHIP_SIENNA_CICHLID:
> -           &nb= sp; dmub_asic =3D DMUB_ASIC_DCN30;
> -           &nb= sp; fw_name_dmub =3D FIRMWARE_SIENNA_CICHLID_DMUB;
> -           &nb= sp; break;
> -     case CHIP_NAVY_FLOUNDER:
> -           &nb= sp; dmub_asic =3D DMUB_ASIC_DCN30;
> -           &nb= sp; fw_name_dmub =3D FIRMWARE_NAVY_FLOUNDER_DMUB;
> +     case IP_VERSION(3, 0, 0):
> +           &nb= sp; if (adev->ip_versions[GC_HWIP] =3D=3D IP_VERSION(10, 3, 0)) {
> +           &nb= sp;         dmub_asic =3D DMUB_ASIC= _DCN30;
> +           &nb= sp;         fw_name_dmub =3D FIRMWA= RE_SIENNA_CICHLID_DMUB;
> +           &nb= sp; } else {
> +           &nb= sp;         dmub_asic =3D DMUB_ASIC= _DCN30;
> +           &nb= sp;         fw_name_dmub =3D FIRMWA= RE_NAVY_FLOUNDER_DMUB;
> +           &nb= sp; }
>            = ;    break;
> -     case CHIP_VANGOGH:
> +     case IP_VERSION(3, 0, 1):
>            = ;    dmub_asic =3D DMUB_ASIC_DCN301;
>            = ;    fw_name_dmub =3D FIRMWARE_VANGOGH_DMUB;
>            = ;    break;
> -     case CHIP_DIMGREY_CAVEFISH:
> +     case IP_VERSION(3, 0, 2):
>            = ;    dmub_asic =3D DMUB_ASIC_DCN302;
>            = ;    fw_name_dmub =3D FIRMWARE_DIMGREY_CAVEFISH_DMUB;
>            = ;    break;
> -     case CHIP_BEIGE_GOBY:
> +     case IP_VERSION(3, 0, 3):
>            = ;    dmub_asic =3D DMUB_ASIC_DCN303;
>            = ;    fw_name_dmub =3D FIRMWARE_BEIGE_GOBY_DMUB;
>            = ;    break;
> -     case CHIP_YELLOW_CARP:
> +     case IP_VERSION(3, 1, 2):
> +     case IP_VERSION(3, 1, 3):
>            = ;    dmub_asic =3D DMUB_ASIC_DCN31;
>            = ;    fw_name_dmub =3D FIRMWARE_YELLOW_CARP_DMUB;
>            = ;    break;
> @@ -2063,10 +2077,9 @@ static int amdgpu_dm_smu_write_watermarks_table= (struct amdgpu_device *adev)
>         * therefore, this func= tion apply to navi10/12/14 but not Renoir
>         * *
>         */
> -     switch(adev->asic_type) {
> -     case CHIP_NAVI10:
> -     case CHIP_NAVI14:
> -     case CHIP_NAVI12:
> +     switch (adev->ip_versions[DCE_HWIP]) { > +     case IP_VERSION(2, 0, 2):
> +     case IP_VERSION(2, 0, 0):
>            = ;    break;
>        default:
>            = ;    return 0;
> @@ -3287,7 +3300,7 @@ static int dce110_register_irq_handlers(struct a= mdgpu_device *adev)
>        int i;
>        unsigned client_id =3D AMDGP= U_IRQ_CLIENTID_LEGACY;
>  
> -     if (adev->asic_type >=3D CHIP_VEGA10)<= br> > +     if (adev->family >=3D AMDGPU_FAMILY_AI= )
>            = ;    client_id =3D SOC15_IH_CLIENTID_DCE;
>  
>        int_params.requested_polarit= y =3D INTERRUPT_POLARITY_DEFAULT;
> @@ -4072,18 +4085,19 @@ static int amdgpu_dm_initialize_drm_device(str= uct amdgpu_device *adev)
>  
>   #if defined(CONFIG_DRM_AMD_DC_DCN)
>        /* Use Outbox interrupt */ > -     switch (adev->asic_type) {
> -     case CHIP_SIENNA_CICHLID:
> -     case CHIP_NAVY_FLOUNDER:
> -     case CHIP_YELLOW_CARP:
> -     case CHIP_RENOIR:
> +     switch (adev->ip_versions[DCE_HWIP]) { > +     case IP_VERSION(3, 0, 0):
> +     case IP_VERSION(3, 1, 2):
> +     case IP_VERSION(3, 1, 3):
> +     case IP_VERSION(2, 1, 0):
>            = ;    if (register_outbox_irq_handlers(dm->adev)) {
>            = ;            DRM_ERR= OR("DM: Failed to initialize IRQ\n");
>            = ;            goto fa= il;
>            = ;    }
>            = ;    break;
>        default:
> -           &nb= sp; DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", ade= v->asic_type);
> +           &nb= sp; DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n"= ,
> +           &nb= sp;            =    adev->ip_versions[DCE_HWIP]);
>        }
>   #endif
>  
> @@ -4171,16 +4185,6 @@ static int amdgpu_dm_initialize_drm_device(stru= ct amdgpu_device *adev)
>            = ;    break;
>   #if defined(CONFIG_DRM_AMD_DC_DCN)
>        case CHIP_RAVEN:
> -     case CHIP_NAVI12:
> -     case CHIP_NAVI10:
> -     case CHIP_NAVI14:
> -     case CHIP_RENOIR:
> -     case CHIP_SIENNA_CICHLID:
> -     case CHIP_NAVY_FLOUNDER:
> -     case CHIP_DIMGREY_CAVEFISH:
> -     case CHIP_BEIGE_GOBY:
> -     case CHIP_VANGOGH:
> -     case CHIP_YELLOW_CARP:
>            = ;    if (dcn10_register_irq_handlers(dm->adev)) {
>            = ;            DRM_ERR= OR("DM: Failed to initialize IRQ\n");
>            = ;            goto fa= il;
> @@ -4188,6 +4192,26 @@ static int amdgpu_dm_initialize_drm_device(stru= ct amdgpu_device *adev)
>            = ;    break;
>   #endif
>        default:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> +           &nb= sp; switch (adev->ip_versions[DCE_HWIP]) {
> +           &nb= sp; case IP_VERSION(2, 0, 2):
> +           &nb= sp; case IP_VERSION(2, 0, 0):
> +           &nb= sp; case IP_VERSION(2, 1, 0):
> +           &nb= sp; case IP_VERSION(3, 0, 0):
> +           &nb= sp; case IP_VERSION(3, 0, 2):
> +           &nb= sp; case IP_VERSION(3, 0, 3):
> +           &nb= sp; case IP_VERSION(3, 0, 1):
> +           &nb= sp; case IP_VERSION(3, 1, 2):
> +           &nb= sp; case IP_VERSION(3, 1, 3):
> +           &nb= sp;         if (dcn10_register_irq_= handlers(dm->adev)) {
> +           &nb= sp;            =      DRM_ERROR("DM: Failed to initialize IRQ\n&quo= t;);
> +           &nb= sp;            =      goto fail;
> +           &nb= sp;         }
> +           &nb= sp;         break;
> +           &nb= sp; default:
> +           &nb= sp;         break;
> +           &nb= sp; }
> +#endif
>            = ;    DRM_ERROR("Unsupported ASIC type: 0x%X\n", ad= ev->asic_type);
>            = ;    goto fail;
>        }
> @@ -4338,38 +4362,43 @@ static int dm_early_init(void *handle)
>            = ;    break;
>   #if defined(CONFIG_DRM_AMD_DC_DCN)
>        case CHIP_RAVEN:
> -     case CHIP_RENOIR:
> -     case CHIP_VANGOGH:
> -           &nb= sp; adev->mode_info.num_crtc =3D 4;
> -           &nb= sp; adev->mode_info.num_hpd =3D 4;
> -           &nb= sp; adev->mode_info.num_dig =3D 4;
> -           &nb= sp; break;
> -     case CHIP_NAVI10:
> -     case CHIP_NAVI12:
> -     case CHIP_SIENNA_CICHLID:
> -     case CHIP_NAVY_FLOUNDER:
> -           &nb= sp; adev->mode_info.num_crtc =3D 6;
> -           &nb= sp; adev->mode_info.num_hpd =3D 6;
> -           &nb= sp; adev->mode_info.num_dig =3D 6;
> -           &nb= sp; break;
> -     case CHIP_YELLOW_CARP:
>            = ;    adev->mode_info.num_crtc =3D 4;
>            = ;    adev->mode_info.num_hpd =3D 4;
>            = ;    adev->mode_info.num_dig =3D 4;
>            = ;    break;
> -     case CHIP_NAVI14:
> -     case CHIP_DIMGREY_CAVEFISH:
> -           &nb= sp; adev->mode_info.num_crtc =3D 5;
> -           &nb= sp; adev->mode_info.num_hpd =3D 5;
> -           &nb= sp; adev->mode_info.num_dig =3D 5;
> -           &nb= sp; break;
> -     case CHIP_BEIGE_GOBY:
> -           &nb= sp; adev->mode_info.num_crtc =3D 2;
> -           &nb= sp; adev->mode_info.num_hpd =3D 2;
> -           &nb= sp; adev->mode_info.num_dig =3D 2;
> -           &nb= sp; break;
>   #endif
>        default:
> +#if defined(CONFIG_DRM_AMD_DC_DCN)
> +           &nb= sp; switch (adev->ip_versions[DCE_HWIP]) {
> +           &nb= sp; case IP_VERSION(2, 0, 2):
> +           &nb= sp; case IP_VERSION(3, 0, 0):
> +           &nb= sp;         adev->mode_info.num_= crtc =3D 6;
> +           &nb= sp;         adev->mode_info.num_= hpd =3D 6;
> +           &nb= sp;         adev->mode_info.num_= dig =3D 6;
> +           &nb= sp;         break;
> +           &nb= sp; case IP_VERSION(2, 0, 0):
> +           &nb= sp; case IP_VERSION(3, 0, 2):
> +           &nb= sp;         adev->mode_info.num_= crtc =3D 5;
> +           &nb= sp;         adev->mode_info.num_= hpd =3D 5;
> +           &nb= sp;         adev->mode_info.num_= dig =3D 5;
> +           &nb= sp;         break;
> +           &nb= sp; case IP_VERSION(3, 0, 3):
> +           &nb= sp;         adev->mode_info.num_= crtc =3D 2;
> +           &nb= sp;         adev->mode_info.num_= hpd =3D 2;
> +           &nb= sp;         adev->mode_info.num_= dig =3D 2;
> +           &nb= sp;         break;
> +           &nb= sp; case IP_VERSION(3, 0, 1):
> +           &nb= sp; case IP_VERSION(2, 1, 0):
> +           &nb= sp; case IP_VERSION(3, 1, 2):
> +           &nb= sp; case IP_VERSION(3, 1, 3):
> +           &nb= sp;         adev->mode_info.num_= crtc =3D 4;
> +           &nb= sp;         adev->mode_info.num_= hpd =3D 4;
> +           &nb= sp;         adev->mode_info.num_= dig =3D 4;
> +           &nb= sp;         break;
> +           &nb= sp; default:
> +           &nb= sp;         break;
> +           &nb= sp; }
> +#endif
>            = ;    DRM_ERROR("Unsupported ASIC type: 0x%X\n", ad= ev->asic_type);
>            = ;    return -EINVAL;
>        }
> @@ -4590,12 +4619,7 @@ fill_gfx9_tiling_info_from_device(const struct = amdgpu_device *adev,
>        tiling_info->gfx9.num_rb_= per_se =3D
>            = ;    adev->gfx.config.gb_addr_config_fields.num_rb_per_se= ;
>        tiling_info->gfx9.shaderE= nable =3D 1;
> -     if (adev->asic_type =3D=3D CHIP_SIENNA_CI= CHLID ||
> -         adev->asic_type = =3D=3D CHIP_NAVY_FLOUNDER ||
> -         adev->asic_type = =3D=3D CHIP_DIMGREY_CAVEFISH ||
> -         adev->asic_type = =3D=3D CHIP_BEIGE_GOBY ||
> -         adev->asic_type = =3D=3D CHIP_YELLOW_CARP ||
> -         adev->asic_type = =3D=3D CHIP_VANGOGH)
> +     if (adev->ip_versions[GC_HWIP] >=3D IP= _VERSION(10, 3, 0))
>            = ;    tiling_info->gfx9.num_pkrs =3D adev->gfx.config.g= b_addr_config_fields.num_pkrs;
>   }
>  
> @@ -5036,7 +5060,7 @@ get_plane_modifiers(const struct amdgpu_device *= adev, unsigned int plane_type, u
>        case AMDGPU_FAMILY_NV:
>        case AMDGPU_FAMILY_VGH:
>        case AMDGPU_FAMILY_YC:
> -           &nb= sp; if (adev->asic_type >=3D CHIP_SIENNA_CICHLID)
> +           &nb= sp; if (adev->ip_versions[GC_HWIP] >=3D IP_VERSION(10, 3, 0))
>            = ;            add_gfx= 10_3_modifiers(adev, mods, &size, &capacity);
>            = ;    else
>            = ;            add_gfx= 10_1_modifiers(adev, mods, &size, &capacity);
> @@ -7647,7 +7671,7 @@ static int amdgpu_dm_plane_init(struct amdgpu_di= splay_manager *dm,
>            = ;    DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
>            = ;    DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
>  
> -     if (dm->adev->asic_type >=3D CHIP_B= ONAIRE &&
> +     if (dm->adev->family >=3D AMDGPU_FA= MILY_CI &&

This doesn't look related.

Thanks,
Lijo

>            plan= e->type !=3D DRM_PLANE_TYPE_CURSOR)
>            = ;    drm_plane_create_rotation_property(plane, DRM_MODE_ROTA= TE_0,
>            = ;            &n= bsp;            = ;            &n= bsp; supported_rotations);
>
--_000_BL1PR12MB5144515BAD46970444CE2749F7A29BL1PR12MB5144namp_--