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charset="us-ascii" Content-Transfer-Encoding: quoted-printable [Public] Fixed locally. ________________________________ From: Lazar, Lijo Sent: Wednesday, September 22, 2021 4:16 AM To: Deucher, Alexander ; amd-gfx@lists.freedeskt= op.org Subject: Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP versio= n checking On 9/21/2021 11:37 PM, Alex Deucher wrote: > Use IP versions rather than asic_type to differentiate > IP version specific features. > > Signed-off-by: Alex Deucher > --- > drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++++++++++------------- > 1 file changed, 18 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/= amd/pm/swsmu/amdgpu_smu.c > index 5f372d353d9d..150cac4ea75c 100644 > --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c > +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c > @@ -455,8 +455,7 @@ static int smu_get_power_num_states(void *handle, > > bool is_support_sw_smu(struct amdgpu_device *adev) > { > - if ((adev->asic_type >=3D CHIP_ARCTURUS) || > - (adev->ip_versions[MP1_HWIP] >=3D IP_VERSION(11, 0, 0))) > + if (adev->ip_versions[MP1_HWIP] >=3D IP_VERSION(11, 0, 0)) > return true; > > return false; > @@ -600,23 +599,19 @@ static int smu_set_funcs(struct amdgpu_device *adev= ) > case IP_VERSION(11, 0, 8): > cyan_skillfish_set_ppt_funcs(smu); > break; > - default: > - switch (adev->asic_type) { > - case CHIP_ARCTURUS: > - adev->pm.pp_feature &=3D ~PP_GFXOFF_MASK; > - arcturus_set_ppt_funcs(smu); > - /* OD is not supported on Arcturus */ > - smu->od_enabled =3Dfalse; > - break; > - case CHIP_ALDEBARAN: > - aldebaran_set_ppt_funcs(smu); > - /* Enable pp_od_clk_voltage node */ > - smu->od_enabled =3D true; > - break; > - default: > - return -EINVAL; > - } > + case IP_VERSION(11, 0, 2): > + adev->pm.pp_feature &=3D ~PP_GFXOFF_MASK; > + arcturus_set_ppt_funcs(smu); > + /* OD is not supported on Arcturus */ > + smu->od_enabled =3Dfalse; > + break; > + case IP_VERSION(13, 0, 2): > + aldebaran_set_ppt_funcs(smu); > + /* Enable pp_od_clk_voltage node */ > + smu->od_enabled =3D true; > break; > + default: > + return -EINVAL; > } > > return 0; > @@ -2288,11 +2283,11 @@ int smu_get_power_limit(void *handle, > } else { > switch (limit_level) { > case SMU_PPT_LIMIT_CURRENT: > - if ((smu->adev->asic_type =3D=3D CHIP_ALDEBARAN) || > - (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION= (11, 0, 7)) || > - (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION= (11, 0, 11)) || > - (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION= (11, 0, 12)) || > - (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION= (11, 0, 13))) > + if ((adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(= 13, 0, 2)) || > + (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(= 11, 0, 7)) || > + (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(= 11, 0, 11)) || > + (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(= 11, 0, 12)) || > + (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(= 11, 0, 13))) Maybe seen/commented before, anyway switch...case Thanks, Lijo > ret =3D smu_get_asic_power_limits(smu, > &smu->curr= ent_power_limit, > NULL, > --_000_BL1PR12MB5144D96B76D54B5648935086F7A29BL1PR12MB5144namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[Public]


Fixed locally.
From: Lazar, Lijo <Lijo.= Lazar@amd.com>
Sent: Wednesday, September 22, 2021 4:16 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@li= sts.freedesktop.org <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 46/66] drm/amdgpu/pm/amdgpu_smu: convert more IP= version checking
 


On 9/21/2021 11:37 PM, Alex Deucher wrote:
> Use IP versions rather than asic_type to differentiate
> IP version specific features.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 41 ++++++++++-= ------------
>   1 file changed, 18 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/d= rm/amd/pm/swsmu/amdgpu_smu.c
> index 5f372d353d9d..150cac4ea75c 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
> @@ -455,8 +455,7 @@ static int smu_get_power_num_states(void *handle,<= br> >  
>   bool is_support_sw_smu(struct amdgpu_device *adev)
>   {
> -     if ((adev->asic_type >=3D CHIP_ARCTURU= S) ||
> -         (adev->ip_version= s[MP1_HWIP] >=3D IP_VERSION(11, 0, 0)))
> +     if (adev->ip_versions[MP1_HWIP] >=3D I= P_VERSION(11, 0, 0))
>            = ;    return true;
>  
>        return false;
> @@ -600,23 +599,19 @@ static int smu_set_funcs(struct amdgpu_device *a= dev)
>        case IP_VERSION(11, 0, 8): >            = ;    cyan_skillfish_set_ppt_funcs(smu);
>            = ;    break;
> -     default:
> -           &nb= sp; switch (adev->asic_type) {
> -           &nb= sp; case CHIP_ARCTURUS:
> -           &nb= sp;         adev->pm.pp_feature = &=3D ~PP_GFXOFF_MASK;
> -           &nb= sp;         arcturus_set_ppt_funcs(= smu);
> -           &nb= sp;         /* OD is not supported = on Arcturus */
> -           &nb= sp;         smu->od_enabled =3Df= alse;
> -           &nb= sp;         break;
> -           &nb= sp; case CHIP_ALDEBARAN:
> -           &nb= sp;         aldebaran_set_ppt_funcs= (smu);
> -           &nb= sp;         /* Enable pp_od_clk_vol= tage node */
> -           &nb= sp;         smu->od_enabled =3D = true;
> -           &nb= sp;         break;
> -           &nb= sp; default:
> -           &nb= sp;         return -EINVAL;
> -           &nb= sp; }
> +     case IP_VERSION(11, 0, 2):
> +           &nb= sp; adev->pm.pp_feature &=3D ~PP_GFXOFF_MASK;
> +           &nb= sp; arcturus_set_ppt_funcs(smu);
> +           &nb= sp; /* OD is not supported on Arcturus */
> +           &nb= sp; smu->od_enabled =3Dfalse;
> +           &nb= sp; break;
> +     case IP_VERSION(13, 0, 2):
> +           &nb= sp; aldebaran_set_ppt_funcs(smu);
> +           &nb= sp; /* Enable pp_od_clk_voltage node */
> +           &nb= sp; smu->od_enabled =3D true;
>            = ;    break;
> +     default:
> +           &nb= sp; return -EINVAL;
>        }
>  
>        return 0;
> @@ -2288,11 +2283,11 @@ int smu_get_power_limit(void *handle,
>        } else {
>            = ;    switch (limit_level) {
>            = ;    case SMU_PPT_LIMIT_CURRENT:
> -           &nb= sp;         if ((smu->adev->a= sic_type =3D=3D CHIP_ALDEBARAN) ||
> -           &nb= sp;            =   (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 7)) ||
> -           &nb= sp;            =   (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 11)) ||
> -           &nb= sp;            =   (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 12)) ||
> -           &nb= sp;            =   (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 13)))
> +           &nb= sp;         if ((adev->ip_versio= ns[MP1_HWIP] =3D=3D IP_VERSION(13, 0, 2)) ||
> +           &nb= sp;            = (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 7)) ||
> +           &nb= sp;            = (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 11)) ||
> +           &nb= sp;            = (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 12)) ||
> +           &nb= sp;            = (adev->ip_versions[MP1_HWIP] =3D=3D IP_VERSION(11, 0, 13)))

Maybe seen/commented before, anyway switch...case

Thanks,
Lijo

>            = ;            &n= bsp;       ret =3D smu_get_asic_power_limits(= smu,
>            = ;            &n= bsp;            = ;            &n= bsp;            = ;  &smu->current_power_limit,
>            = ;            &n= bsp;            = ;            &n= bsp;            = ;  NULL,
>
--_000_BL1PR12MB5144D96B76D54B5648935086F7A29BL1PR12MB5144namp_--