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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: BN9PR12MB5145.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 247e0a71-9c3b-437f-5d4f-08da31c5959c X-MS-Exchange-CrossTenant-originalarrivaltime: 09 May 2022 14:09:51.4248 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: zyopOc8gyNfAIc2AlMzhjkx7NLSs7XYT8htEPgF4XaFKKvpacwSIFwnEtN4OYX+W4iwWXqGiqeNCHWmsObTq9A== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR12MB1268 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Wang, Chao-kai \(Stylon\)" , "Li, Sun peng \(Leo\)" , "Lakha, Bhawanpreet" , "Zhuo, Qingqing \(Lillian\)" , "Siqueira, Rodrigo" , "Li, Roman" , "Chiu, Solomon" , "Zuo, Jerry" , "Pillai, Aurabindo" , "Lin, Wayne" , "Wentland, Harry" , "Gutierrez, Agustin" , "Kotarac, Pavle" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [AMD Official Use Only - General] Hi Chandan, Replied in-mail. Thanks DZ From: VURDIGERENATARAJ, CHANDAN Sent: Monday, May 9, 2022 4:42 AM To: Zhang, Dingchen (David) ; amd-gfx@lists.freedes= ktop.org Cc: Wang, Chao-kai (Stylon) ; Li, Sun peng (Leo) ; Wentland, Harry ; Zhuo, Qingqing (= Lillian) ; Siqueira, Rodrigo ; Li, Roman ; Chiu, Solomon ; Zu= o, Jerry ; Pillai, Aurabindo ;= Lin, Wayne ; Lakha, Bhawanpreet ; Gutierrez, Agustin ; Kotarac, Pavle Subject: RE: [PATCH 14/17] drm/amd/display: add shared helpers to update ps= r config fields to power module Hi >[why] >Currently the amdgpu DM psr configuration parameters are hardcoded before = feeding into the DC helper to setup PSR. We would define a helper >which is= to calculate parts of the psr config fields to avoid hard-coding. > >[how] >To make helper shareable, declare and define the helper in the module_help= er, to set/update below fields: >- psr remote buffer setup time >- sdp tx line number deadline >- line time in us >- su_y_granularity >- su_granularity_required >- psr_frame_capture_indication_req >- psr_exit_link_training_required > >add another helper to check given the stream context, if there is only one= stream and the output is eDP panel connected. > >Signed-off-by: David Zhang >--- > .../amd/display/modules/power/power_helpers.c | 73 +++++++++++++++++++ .= ../amd/display/modules/power/power_helpers.h | 6 ++ > 2 files changed, 79 insertions(+) > >diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/d= rivers/gpu/drm/amd/display/modules/power/power_helpers.c >index 97928d4c3b9a..1be4fcfa578a 100644 >--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c >+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c >@@ -822,3 +822,76 @@ bool is_psr_su_specific_panel(struct dc_link *link) > > return false; > } >+ >+/** >+ * mod_power_calc_psr_configs() - calculate/update generic psr configurat= ion fields. >+ * @psr_config: [output], psr configuration structure to be updated >+ * @link: [input] dc link pointer >+ * @stream: [input] dc stream state pointer >+ * >+ * calculate and update the psr configuration fields that are not DM >+specific, i.e. such >+ * fields which are based on DPCD caps or timing information. To setup >+PSR in DMUB FW, >+ * this helper is assumed to be called before the call of the DC helper d= c_link_setup_psr(). >+ * >+ * PSR config fields to be updated within the helper: >+ * - psr_rfb_setup_time >+ * - psr_sdp_transmit_line_num_deadline >+ * - line_time_in_us >+ * - su_y_granularity >+ * - su_granularity_required >+ * - psr_frame_capture_indication_req >+ * - psr_exit_link_training_required >+ * >+ * PSR config fields that are DM specific and NOT updated within the help= er: >+ * - allow_smu_optimizations >+ * - allow_multi_disp_optimizations >+ */ >+void mod_power_calc_psr_configs(struct psr_config *psr_config, >+ struct dc_link *link, >+ const struct dc_stream_state *stream) { >+ unsigned int num_vblank_lines =3D 0; >+ unsigned int vblank_time_in_us =3D 0; >+ unsigned int sdp_tx_deadline_in_us =3D 0; >+ unsigned int line_time_in_us =3D 0; >+ struct dpcd_caps *dpcd_caps =3D &link->dpcd_caps; >+ const int psr_setup_time_step_in_us =3D 55; /* refer to eDP s= pec DPCD 0x071h */ >+ >+ /* timing parameters */ >+ num_vblank_lines =3D stream->timing.v_total - >+ stream->timing.v_addressable - >+ stream->timing.v_border_top - >+ stream->timing.v_border_bottom; >+ >+ vblank_time_in_us =3D (stream->timing.h_total * num_vblank_lines * = 1000) >+/ (stream->timing.pix_clk_100hz / 10); >+ >+ line_time_in_us =3D ((stream->timing.h_total * 1000) / >+(stream->timing.pix_clk_100hz / 10)) + 1; >+ >+ /* psr configuration fields */ >+ psr_config->psr_rfb_setup_time =3D >+ (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME)= * Is this " dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME" always exp= ected to be less than '6'. What does this 6 indicate here? *** This is as per the eDP 1.5 spec, DPCD reg at 0x00071h, i.e. the PSR Cap reg= . (page 377 of 459) the PSR_SETUP_TIME is represented by 3 bits and interpreted as - 000b <--> 330 (us) - 001b <--> 275 (us) - 010b <--> 220 (us) - 011b <--> 165 (us) - 100b <--> 110 (us) - 101b <--> 055 (us) - 110b <--> 000 (us) Since the base 0us interpreted by '6', so the actual psr setup time will be= "(6 - psr_setup_time_in_binary) * 55 (us)". That's where the '6' coming fr= om. *** >+psr_setup_time_step_in_us; >+ >+ if (psr_config->psr_rfb_setup_time > vblank_time_in_us) { >+ link->psr_settings.psr_frame_capture_indication_req =3D tru= e; >+ link->psr_settings.psr_sdp_transmit_line_num_deadline =3D n= um_vblank_lines; >+ } else { >+ sdp_tx_deadline_in_us =3D vblank_time_in_us - >+psr_config->psr_rfb_setup_time; >+ >+ /* Set the last possible line SDP may be transmitted withou= t violating the RFB setup time */ >+ link->psr_settings.psr_frame_capture_indication_req =3D fal= se; >+ link->psr_settings.psr_sdp_transmit_line_num_deadline =3D s= dp_tx_deadline_in_us / line_time_in_us; >+ } >+ >+ psr_config->psr_sdp_transmit_line_num_deadline =3D link->psr_settin= gs.psr_sdp_transmit_line_num_deadline; >+ psr_config->line_time_in_us =3D line_time_in_us; >+ psr_config->su_y_granularity =3D dpcd_caps->psr_info.psr2_su_y_gran= ularity_cap; >+ psr_config->su_granularity_required =3D dpcd_caps->psr_info.psr_dpc= d_caps.bits.SU_GRANULARITY_REQUIRED; >+ psr_config->psr_frame_capture_indication_req =3D link->psr_settings= .psr_frame_capture_indication_req; >+ psr_config->psr_exit_link_training_required =3D >+ >+!link->dpcd_caps.psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_ >+REQUIRED; >+} >+ >+bool mod_power_only_edp(const struct dc_state *context, const struct >+dc_stream_state *stream) { >+ return context && context->stream_count =3D=3D 1 && >+dc_is_embedded_signal(stream->signal); >+} >diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h b/d= rivers/gpu/drm/amd/display/modules/power/power_helpers.h >index 1a634d8c78c5..316452e9dbc9 100644 >--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.h >+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.h >@@ -27,6 +27,7 @@ > > #include "dc/inc/hw/dmcu.h" > #include "dc/inc/hw/abm.h" >+#include "dc/inc/core_types.h" > > struct resource_pool; > >@@ -53,4 +54,9 @@ bool dmub_init_abm_config(struct resource_pool *res_pool= , > unsigned int inst); > > bool is_psr_su_specific_panel(struct dc_link *link); >+void mod_power_calc_psr_configs(struct psr_config *psr_config, >+ struct dc_link *link, >+ const struct dc_stream_state *stream); bool mod_power_only_= edp(const >+struct dc_state *context, >+ const struct dc_stream_state *stream); > #endif /* MODULES_POWER_POWER_HELPERS_H_ */ >-- >2.25.1 >