From: Alex Deucher <alexdeucher@gmail.com>
To: Tom St Denis <tom.stdenis@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)
Date: Wed, 25 Mar 2020 16:10:26 -0400 [thread overview]
Message-ID: <CADnq5_O6tv-V5iOKwjEVDJo6hU4i_=Y3O0fzju0XqTBb+hAT3w@mail.gmail.com> (raw)
In-Reply-To: <20200325192221.717578-1-tom.stdenis@amd.com>
On Wed, Mar 25, 2020 at 3:22 PM Tom St Denis <tom.stdenis@amd.com> wrote:
>
> The PWR block was merged into the SMUIO block by revision 12 so we add
> that to the smuio_12_0_0 headers.
>
> (v2): Drop nonsensical smuio_10_0_0 header
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
> .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h | 5 +++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> index 327b4d09f66d..9bf73284ad73 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> @@ -24,4 +24,7 @@
> #define mmSMUIO_GFX_MISC_CNTL 0x00c8
> #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
>
> +#define mmPWR_MISC_CNTL_STATUS 0x0183
> +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX 1
> +
> #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> index d815452cfd15..26556fa3d054 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> @@ -24,5 +24,10 @@
> //SMUIO_GFX_MISC_CNTL
> #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
> #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
> +//PWR_MISC_CNTL_STATUS
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L
>
> #endif
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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prev parent reply other threads:[~2020-03-25 20:10 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-25 19:22 [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2) Tom St Denis
2020-03-25 19:28 ` Deucher, Alexander
2020-03-25 19:38 ` Tom St Denis
2020-03-25 20:10 ` Alex Deucher [this message]
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