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* [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)
@ 2020-03-25 19:22 Tom St Denis
  2020-03-25 19:28 ` Deucher, Alexander
  2020-03-25 20:10 ` Alex Deucher
  0 siblings, 2 replies; 4+ messages in thread
From: Tom St Denis @ 2020-03-25 19:22 UTC (permalink / raw)
  To: amd-gfx; +Cc: Tom St Denis

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h    | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL                                                                          0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                                                                 0
 
+#define mmPWR_MISC_CNTL_STATUS                                                                         0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX                                                                1
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK                                                           0x00000006L
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT                                                         0x1
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT                                                      0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT                                                        0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK                                                        0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK                                                          0x00000006L
 
 #endif
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)
  2020-03-25 19:22 [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2) Tom St Denis
@ 2020-03-25 19:28 ` Deucher, Alexander
  2020-03-25 19:38   ` Tom St Denis
  2020-03-25 20:10 ` Alex Deucher
  1 sibling, 1 reply; 4+ messages in thread
From: Deucher, Alexander @ 2020-03-25 19:28 UTC (permalink / raw)
  To: StDenis, Tom, amd-gfx

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[AMD Public Use]

While you are at it, can you clean up the local defines of these registers in
drivers/gpu/drm/amd/powerplay/hwmgr/smu10_hwmgr.c
drivers/gpu/drm/amd/powerplay/smu_v12_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
and verify that the appropriate offset is used for both Renoir and raven?

Alex

________________________________
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf of Tom St Denis <tom.stdenis@amd.com>
Sent: Wednesday, March 25, 2020 3:22 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: StDenis, Tom <Tom.StDenis@amd.com>
Subject: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
---
 .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
 .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h    | 5 +++++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
index 327b4d09f66d..9bf73284ad73 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
@@ -24,4 +24,7 @@
 #define mmSMUIO_GFX_MISC_CNTL                                                                          0x00c8
 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                                                                 0

+#define mmPWR_MISC_CNTL_STATUS                                                                         0x0183
+#define mmPWR_MISC_CNTL_STATUS_BASE_IDX                                                                1
+
 #endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
index d815452cfd15..26556fa3d054 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
@@ -24,5 +24,10 @@
 //SMUIO_GFX_MISC_CNTL
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK                                                           0x00000006L
 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT                                                         0x1
+//PWR_MISC_CNTL_STATUS
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT                                                      0x0
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT                                                        0x1
+#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK                                                        0x00000001L
+#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK                                                          0x00000006L

 #endif
--
2.25.1

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^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)
  2020-03-25 19:28 ` Deucher, Alexander
@ 2020-03-25 19:38   ` Tom St Denis
  0 siblings, 0 replies; 4+ messages in thread
From: Tom St Denis @ 2020-03-25 19:38 UTC (permalink / raw)
  To: Deucher, Alexander, amd-gfx

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)
  2020-03-25 19:22 [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2) Tom St Denis
  2020-03-25 19:28 ` Deucher, Alexander
@ 2020-03-25 20:10 ` Alex Deucher
  1 sibling, 0 replies; 4+ messages in thread
From: Alex Deucher @ 2020-03-25 20:10 UTC (permalink / raw)
  To: Tom St Denis; +Cc: amd-gfx list

On Wed, Mar 25, 2020 at 3:22 PM Tom St Denis <tom.stdenis@amd.com> wrote:
>
> The PWR block was merged into the SMUIO block by revision 12 so we add
> that to the smuio_12_0_0 headers.
>
> (v2): Drop nonsensical smuio_10_0_0 header
>
> Signed-off-by: Tom St Denis <tom.stdenis@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  .../gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h | 3 +++
>  .../drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h    | 5 +++++
>  2 files changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> index 327b4d09f66d..9bf73284ad73 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
> @@ -24,4 +24,7 @@
>  #define mmSMUIO_GFX_MISC_CNTL                                                                          0x00c8
>  #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX                                                                 0
>
> +#define mmPWR_MISC_CNTL_STATUS                                                                         0x0183
> +#define mmPWR_MISC_CNTL_STATUS_BASE_IDX                                                                1
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> index d815452cfd15..26556fa3d054 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
> @@ -24,5 +24,10 @@
>  //SMUIO_GFX_MISC_CNTL
>  #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK                                                           0x00000006L
>  #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT                                                         0x1
> +//PWR_MISC_CNTL_STATUS
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT                                                      0x0
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT                                                        0x1
> +#define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK                                                        0x00000001L
> +#define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK                                                          0x00000006L
>
>  #endif
> --
> 2.25.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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2020-03-25 19:22 [PATCH] drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2) Tom St Denis
2020-03-25 19:28 ` Deucher, Alexander
2020-03-25 19:38   ` Tom St Denis
2020-03-25 20:10 ` Alex Deucher

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