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boundary="===============0361578157==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0361578157== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_CH0PR12MB528457F2643C9A68B6CD21E78B499CH0PR12MB5284namp_" --_000_CH0PR12MB528457F2643C9A68B6CD21E78B499CH0PR12MB5284namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - Internal Distribution Only] This patch is a related change for the MST null pointer deref regression, s= o will be dropped. -- Thanks & Regards, Aurabindo Pillai ________________________________ From: Aurabindo Pillai Sent: Friday, April 16, 2021 10:34 AM To: amd-gfx@lists.freedesktop.org Cc: Wentland, Harry ; Li, Sun peng (Leo) ; Lakha, Bhawanpreet ; Siqueira, Rodri= go ; Pillai, Aurabindo = ; Zhuo, Qingqing ; Brol, Eryk ; R= , Bindu ; Jacob, Anson ; Zhang, Dingc= hen (David) ; Zhang, Dingchen (David) Subject: [PATCH 14/19] drm/amd/display: fix HDCP drm prop update for MST From: "Dingchen (David) Zhang" [why] For MST topology with 1 physical link and multiple connectors (>=3D2), e.g. daisy cahined MST + SST, or 1-to-multi MST hub, if userspace set to enable the HDCP simultaneously on all connected outputs, the commit tail iteratively call the hdcp_update_display() for each display (connector). However, the hdcp workqueue data structure for each link has only one DM connector and encryption status members, which means the work queue of property_validate/update() would only be triggered for the last connector within this physical link, and therefore the HDCP property value of other connectors would stay on DESIRED instead of switching to ENABLED, which is NOT as expected. [how] Use array of MAX_NUM_OF_DISPLAY for both aconnector and encryption status in hdcp workqueue data structure for each physical link. For property validate/update work queue, we iterates over the array and do similar operation/check for each connected display. Signed-off-by: Dingchen (David) Zhang Reviewed-by: Dingchen Zhang Acked-by: Aurabindo Pillai --- .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 109 +++++++++++++----- .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h | 6 +- 2 files changed, 81 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 50f6b3a86931..2ec076af9e89 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -171,9 +171,10 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_w= ork, struct mod_hdcp_display *display =3D &hdcp_work[link_index].displa= y; struct mod_hdcp_link *link =3D &hdcp_work[link_index].link; struct mod_hdcp_display_query query; + unsigned int conn_index =3D aconnector->base.index; mutex_lock(&hdcp_w->mutex); - hdcp_w->aconnector =3D aconnector; + hdcp_w->aconnector[conn_index] =3D aconnector; query.display =3D NULL; mod_hdcp_query_display(&hdcp_w->hdcp, aconnector->base.index, &que= ry); @@ -205,7 +206,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_wo= rk, msecs_to_jiffies(DRM_HDCP_CH= ECK_PERIOD_MS)); } else { display->adjust.disable =3D MOD_HDCP_DISPLAY_DISAB= LE_AUTHENTICATION; - hdcp_w->encryption_status =3D MOD_HDCP_ENCRYPTION_S= TATUS_HDCP_OFF; + hdcp_w->encryption_status[conn_index] =3D MOD_HDCP_= ENCRYPTION_STATUS_HDCP_OFF; cancel_delayed_work(&hdcp_w->property_validate_dwo= rk); } @@ -224,9 +225,10 @@ static void hdcp_remove_display(struct hdcp_workqueue = *hdcp_work, { struct hdcp_workqueue *hdcp_w =3D &hdcp_work[link_index]; struct drm_connector_state *conn_state =3D aconnector->base.state; + unsigned int conn_index =3D aconnector->base.index; mutex_lock(&hdcp_w->mutex); - hdcp_w->aconnector =3D aconnector; + hdcp_w->aconnector[conn_index] =3D aconnector; /* the removal of display will invoke auth reset -> hdcp destroy a= nd * we'd expect the CP prop changed back to DESIRED if at the time = ENABLED. @@ -247,13 +249,16 @@ static void hdcp_remove_display(struct hdcp_workqueue= *hdcp_work, void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned int lin= k_index) { struct hdcp_workqueue *hdcp_w =3D &hdcp_work[link_index]; + unsigned int conn_index; mutex_lock(&hdcp_w->mutex); mod_hdcp_reset_connection(&hdcp_w->hdcp, &hdcp_w->output); cancel_delayed_work(&hdcp_w->property_validate_dwork); - hdcp_w->encryption_status =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; + + for (conn_index =3D 0; conn_index < MAX_NUM_OF_DISPLAYS; ++conn_ind= ex) + hdcp_w->encryption_status[conn_index] =3D MOD_HDCP_ENCRYPTI= ON_STATUS_HDCP_OFF; process_output(hdcp_w); @@ -290,38 +295,67 @@ static void event_callback(struct work_struct *work) } + +static struct amdgpu_dm_connector *find_first_connected_output(struct hdcp= _workqueue *hdcp_work) +{ + unsigned int conn_index; + + for (conn_index =3D 0; conn_index < MAX_NUM_OF_DISPLAYS; ++conn_ind= ex) { + if (hdcp_work->aconnector[conn_index]) + return hdcp_work->aconnector[conn_index]; + } + + return NULL; +} + static void event_property_update(struct work_struct *work) { struct hdcp_workqueue *hdcp_work =3D container_of(work, struct hdc= p_workqueue, property_update_work); - struct amdgpu_dm_connector *aconnector =3D hdcp_work->aconnector; - struct drm_device *dev =3D hdcp_work->aconnector->base.dev; + struct amdgpu_dm_connector *aconnector =3D find_first_connected_out= put(hdcp_work); + struct drm_device *dev; long ret; + unsigned int conn_index; + struct drm_connector *connector; + struct drm_connector_state *conn_state; + + if (!aconnector) + return; + + dev =3D aconnector->base.dev; drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); mutex_lock(&hdcp_work->mutex); + for (conn_index =3D 0; conn_index < MAX_NUM_OF_DISPLAYS; ++conn_ind= ex) { + aconnector =3D hdcp_work->aconnector[conn_index]; + + if (!aconnector) + continue; - if (aconnector->base.state->commit) { - ret =3D wait_for_completion_interruptible_timeout(&aconnect= or->base.state->commit->hw_done, 10 * HZ); + connector =3D &aconnector->base; + conn_state =3D aconnector->base.state; + if (conn_state->commit) { + ret =3D wait_for_completion_interruptible_timeout(&= conn_state->commit->hw_done, 10 * HZ); - if (ret =3D=3D 0) { - DRM_ERROR("HDCP state unknown! Setting it to DESIRE= D"); - hdcp_work->encryption_status =3D MOD_HDCP_ENCRYPTIO= N_STATUS_HDCP_OFF; + if (ret =3D=3D 0) { + DRM_ERROR("HDCP state unknown! Setting it t= o DESIRED"); + hdcp_work->encryption_status[conn_index] = =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; + } } - } - if (hdcp_work->encryption_status !=3D MOD_HDCP_ENCRYPTION_STATUS_HD= CP_OFF) { - if (aconnector->base.state->hdcp_content_type =3D=3D DRM_MO= DE_HDCP_CONTENT_TYPE0 && - hdcp_work->encryption_status <=3D MOD_HDCP_ENCRYPTION_S= TATUS_HDCP2_TYPE0_ON) - drm_hdcp_update_content_protection(&aconnector->bas= e, DRM_MODE_CONTENT_PROTECTION_ENABLED); - else if (aconnector->base.state->hdcp_content_type =3D=3D D= RM_MODE_HDCP_CONTENT_TYPE1 && - hdcp_work->encryption_status =3D=3D MOD_HDCP_ENCRY= PTION_STATUS_HDCP2_TYPE1_ON) - drm_hdcp_update_content_protection(&aconnector->bas= e, DRM_MODE_CONTENT_PROTECTION_ENABLED); - } else { - drm_hdcp_update_content_protection(&aconnector->base, DRM_M= ODE_CONTENT_PROTECTION_DESIRED); - } + if (hdcp_work->encryption_status[conn_index] !=3D MOD_HDCP_= ENCRYPTION_STATUS_HDCP_OFF) { + if (conn_state->hdcp_content_type =3D=3D DRM_MODE_H= DCP_CONTENT_TYPE0 && + hdcp_work->encryption_status[conn_index] <=3D M= OD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON) + drm_hdcp_update_content_protection(connecto= r, DRM_MODE_CONTENT_PROTECTION_ENABLED); + else if (conn_state->hdcp_content_type =3D=3D DRM_M= ODE_HDCP_CONTENT_TYPE1 && + hdcp_work->encryption_status[conn_index] = =3D=3D MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON) + drm_hdcp_update_content_protection(connecto= r, DRM_MODE_CONTENT_PROTECTION_ENABLED); + } else { + drm_hdcp_update_content_protection(connector, DRM_M= ODE_CONTENT_PROTECTION_DESIRED); + } + } mutex_unlock(&hdcp_work->mutex); drm_modeset_unlock(&dev->mode_config.connection_mutex); @@ -332,19 +366,28 @@ static void event_property_validate(struct work_struc= t *work) struct hdcp_workqueue *hdcp_work =3D container_of(to_delayed_work(work), struct hdcp_workqueue,= property_validate_dwork); struct mod_hdcp_display_query query; - struct amdgpu_dm_connector *aconnector =3D hdcp_work->aconnector; - - if (!aconnector) - return; + struct amdgpu_dm_connector *aconnector; + unsigned int conn_index; mutex_lock(&hdcp_work->mutex); - query.encryption_status =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; - mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.index, &q= uery); + for (conn_index =3D 0; conn_index < MAX_NUM_OF_DISPLAYS; ++conn_ind= ex) { + aconnector =3D hdcp_work->aconnector[conn_index]; + + if (!aconnector) + continue; + + query.encryption_status =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP= _OFF; + mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->base.i= ndex, &query); - if (query.encryption_status !=3D hdcp_work->encryption_status) { - hdcp_work->encryption_status =3D query.encryption_status; - schedule_work(&hdcp_work->property_update_work); + pr_debug("[HDCP_DM] display %d, CP %u, (query->enc_st, work= ->enc_st): (%d, %d)\n", + aconnector->base.index, aconnector->base.state->co= ntent_protection, + query.encryption_status, hdcp_work->encryption_sta= tus[conn_index]); + + if (query.encryption_status !=3D hdcp_work->encryption_stat= us[conn_index]) { + hdcp_work->encryption_status[conn_index] =3D query.= encryption_status; + schedule_work(&hdcp_work->property_update_work); + } } mutex_unlock(&hdcp_work->mutex); @@ -655,6 +698,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct am= dgpu_device *adev, struct hdcp_work[i].hdcp.config.ddc.funcs.read_i2c =3D lp_read_i2= c; hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd =3D lp_write= _dpcd; hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd =3D lp_read_d= pcd; + + memset(hdcp_work[i].aconnector, 0, sizeof(struct amdgpu_dm_= connector *) * MAX_NUM_OF_DISPLAYS); + memset(hdcp_work[i].encryption_status, 0, + sizeof(enum mod_hdcp_encryption_status) * MAX_NUM_O= F_DISPLAYS); } cp_psp->funcs.update_stream_config =3D update_config; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h index 09294ff122fe..570863160d60 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h @@ -1,5 +1,5 @@ /* - * Copyright 2019 Advanced Micro Devices, Inc. + * Copyright (C) 2019-2020 Advanced Micro Devices, Inc. All rights reserve= d. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software= "), @@ -43,7 +43,7 @@ struct hdcp_workqueue { struct delayed_work callback_dwork; struct delayed_work watchdog_timer_dwork; struct delayed_work property_validate_dwork; - struct amdgpu_dm_connector *aconnector; + struct amdgpu_dm_connector *aconnector[MAX_NUM_OF_DISPLAYS]; struct mutex mutex; struct mod_hdcp hdcp; @@ -51,7 +51,7 @@ struct hdcp_workqueue { struct mod_hdcp_display display; struct mod_hdcp_link link; - enum mod_hdcp_encryption_status encryption_status; + enum mod_hdcp_encryption_status encryption_status[MAX_NUM_OF_DISPLA= YS]; uint8_t max_link; uint8_t *srm; -- 2.31.1 --_000_CH0PR12MB528457F2643C9A68B6CD21E78B499CH0PR12MB5284namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only - Internal Distribution Only]


This patch is a related change for the MST null pointer deref regression, s= o will be dropped.

--

Thanks & Regards,
Aurabindo Pillai
From: Aurabindo Pillai <= aurabindo.pillai@amd.com>
Sent: Friday, April 16, 2021 10:34 AM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org&= gt;
Cc: Wentland, Harry <Harry.Wentland@amd.com>; Li, Sun peng (Le= o) <Sunpeng.Li@amd.com>; Lakha, Bhawanpreet <Bhawanpreet.Lakha@amd= .com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Pillai, Aurab= indo <Aurabindo.Pillai@amd.com>; Zhuo, Qingqing <Qingqing.Zhuo@amd= .com>; Brol, Eryk <Eryk.Brol@amd.com>; R, Bindu <Bindu.R@amd.com>; Ja= cob, Anson <Anson.Jacob@amd.com>; Zhang, Dingchen (David) <Dingche= n.Zhang@amd.com>; Zhang, Dingchen (David) <Dingchen.Zhang@amd.com>=
Subject: [PATCH 14/19] drm/amd/display: fix HDCP drm prop update for= MST
 
From: "Dingchen (David) Zhang" <dingc= hen.zhang@amd.com>

[why]
For MST topology with 1 physical link and multiple connectors (>=3D2), e.g. daisy cahined MST + SST, or 1-to-multi MST hub, if userspace
set to enable the HDCP simultaneously on all connected outputs, the
commit tail iteratively call the hdcp_update_display() for each
display (connector). However, the hdcp workqueue data structure for
each link has only one DM connector and encryption status members,
which means the work queue of property_validate/update() would only
be triggered for the last connector within this physical link, and
therefore the HDCP property value of other connectors would stay on
DESIRED instead of switching to ENABLED, which is NOT as expected.

[how]
Use array of MAX_NUM_OF_DISPLAY for both aconnector and encryption
status in hdcp workqueue data structure for each physical link.
For property validate/update work queue, we iterates over the array
and do similar operation/check for each connected display.

Signed-off-by: Dingchen (David) Zhang <dingchen.zhang@amd.com>
Reviewed-by: Dingchen Zhang <Dingchen.Zhang@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
---
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.c    | 109 ++= +++++++++++-----
 .../amd/display/amdgpu_dm/amdgpu_dm_hdcp.h    | &= nbsp; 6 +-
 2 files changed, 81 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
index 50f6b3a86931..2ec076af9e89 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
@@ -171,9 +171,10 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_w= ork,
         struct mod_hdcp_display *d= isplay =3D &hdcp_work[link_index].display;
         struct mod_hdcp_link *link= =3D &hdcp_work[link_index].link;
         struct mod_hdcp_display_qu= ery query;
+       unsigned int conn_index =3D aconnecto= r->base.index;
 
         mutex_lock(&hdcp_w->= ;mutex);
-       hdcp_w->aconnector =3D aconnector;=
+       hdcp_w->aconnector[conn_index] =3D= aconnector;
 
         query.display =3D NULL;          mod_hdcp_query_display(&am= p;hdcp_w->hdcp, aconnector->base.index, &query);
@@ -205,7 +206,7 @@ void hdcp_update_display(struct hdcp_workqueue *hdcp_wo= rk,
            &nb= sp;            =             &nb= sp;         msecs_to_jiffies(DRM_HD= CP_CHECK_PERIOD_MS));
            &nb= sp;    } else {
            &nb= sp;            displ= ay->adjust.disable =3D MOD_HDCP_DISPLAY_DISABLE_AUTHENTICATION;
-            &n= bsp;          hdcp_w->encry= ption_status =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+            &n= bsp;          hdcp_w->encry= ption_status[conn_index] =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
            &nb= sp;            cance= l_delayed_work(&hdcp_w->property_validate_dwork);
            &nb= sp;    }
 
@@ -224,9 +225,10 @@ static void hdcp_remove_display(struct hdcp_workqueue = *hdcp_work,
 {
         struct hdcp_workqueue *hdc= p_w =3D &hdcp_work[link_index];
         struct drm_connector_state= *conn_state =3D aconnector->base.state;
+       unsigned int conn_index =3D aconnecto= r->base.index;
 
         mutex_lock(&hdcp_w->= ;mutex);
-       hdcp_w->aconnector =3D aconnector;=
+       hdcp_w->aconnector[conn_index] =3D= aconnector;
 
         /* the removal of display = will invoke auth reset -> hdcp destroy and
          * we'd expect the CP= prop changed back to DESIRED if at the time ENABLED.
@@ -247,13 +249,16 @@ static void hdcp_remove_display(struct hdcp_workqueue= *hdcp_work,
 void hdcp_reset_display(struct hdcp_workqueue *hdcp_work, unsigned in= t link_index)
 {
         struct hdcp_workqueue *hdc= p_w =3D &hdcp_work[link_index];
+       unsigned int conn_index;
 
         mutex_lock(&hdcp_w->= ;mutex);
 
         mod_hdcp_reset_connection(= &hdcp_w->hdcp,  &hdcp_w->output);
 
         cancel_delayed_work(&h= dcp_w->property_validate_dwork);
-       hdcp_w->encryption_status =3D MOD_= HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+
+       for (conn_index =3D 0; conn_index <= ; MAX_NUM_OF_DISPLAYS; ++conn_index)
+            &n= bsp;  hdcp_w->encryption_status[conn_index] =3D MOD_HDCP_ENCRYPTION= _STATUS_HDCP_OFF;
 
         process_output(hdcp_w);  
@@ -290,38 +295,67 @@ static void event_callback(struct work_struct *work)<= br>  
 
 }
+
+static struct amdgpu_dm_connector *find_first_connected_output(struct hdcp= _workqueue *hdcp_work)
+{
+       unsigned int conn_index;
+
+       for (conn_index =3D 0; conn_index <= ; MAX_NUM_OF_DISPLAYS; ++conn_index) {
+            &n= bsp;  if (hdcp_work->aconnector[conn_index])
+            &n= bsp;          return hdcp_work= ->aconnector[conn_index];
+       }
+
+       return NULL;
+}
+
 static void event_property_update(struct work_struct *work)
 {
 
         struct hdcp_workqueue *hdc= p_work =3D container_of(work, struct hdcp_workqueue, property_update_work);=
-       struct amdgpu_dm_connector *aconnecto= r =3D hdcp_work->aconnector;
-       struct drm_device *dev =3D hdcp_work-= >aconnector->base.dev;
+       struct amdgpu_dm_connector *aconnecto= r =3D find_first_connected_output(hdcp_work);
+       struct drm_device *dev;
         long ret;
+       unsigned int conn_index;
+       struct drm_connector *connector;
+       struct drm_connector_state *conn_stat= e;
+
+       if (!aconnector)
+            &n= bsp;  return;
+
+       dev =3D aconnector->base.dev;
 
         drm_modeset_lock(&dev-= >mode_config.connection_mutex, NULL);
         mutex_lock(&hdcp_work-= >mutex);
 
+       for (conn_index =3D 0; conn_index <= ; MAX_NUM_OF_DISPLAYS; ++conn_index) {
+            &n= bsp;  aconnector =3D hdcp_work->aconnector[conn_index];
+
+            &n= bsp;  if (!aconnector)
+            &n= bsp;          continue;
 
-       if (aconnector->base.state->com= mit) {
-            &n= bsp;  ret =3D wait_for_completion_interruptible_timeout(&aconnecto= r->base.state->commit->hw_done, 10 * HZ);
+            &n= bsp;  connector =3D &aconnector->base;
+            &n= bsp;  conn_state =3D aconnector->base.state;
+            &n= bsp;  if (conn_state->commit) {
+            &n= bsp;          ret =3D wait_for= _completion_interruptible_timeout(&conn_state->commit->hw_done, 1= 0 * HZ);
 
-            &n= bsp;  if (ret =3D=3D 0) {
-            &n= bsp;          DRM_ERROR("= HDCP state unknown! Setting it to DESIRED");
-            &n= bsp;          hdcp_work->en= cryption_status =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+            &n= bsp;          if (ret =3D=3D 0= ) {
+            &n= bsp;            = ;      DRM_ERROR("HDCP state unknown! Setting= it to DESIRED");
+            &n= bsp;            = ;      hdcp_work->encryption_status[conn_index]= =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;
+            &n= bsp;          }
            &nb= sp;    }
-       }
 
-       if (hdcp_work->encryption_status != =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) {
-            &n= bsp;  if (aconnector->base.state->hdcp_content_type =3D=3D DRM_M= ODE_HDCP_CONTENT_TYPE0 &&
-            &n= bsp;      hdcp_work->encryption_status <=3D = MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE0_ON)
-            &n= bsp;          drm_hdcp_update_= content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_EN= ABLED);
-            &n= bsp;  else if (aconnector->base.state->hdcp_content_type =3D=3D = DRM_MODE_HDCP_CONTENT_TYPE1 &&
-            &n= bsp;           hdcp_work-= >encryption_status =3D=3D MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
-            &n= bsp;          drm_hdcp_update_= content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_EN= ABLED);
-       } else {
-            &n= bsp;  drm_hdcp_update_content_protection(&aconnector->base, DRM= _MODE_CONTENT_PROTECTION_DESIRED);
-       }
+            &n= bsp;  if (hdcp_work->encryption_status[conn_index] !=3D MOD_HDCP_EN= CRYPTION_STATUS_HDCP_OFF) {
+            &n= bsp;          if (conn_state-&= gt;hdcp_content_type =3D=3D DRM_MODE_HDCP_CONTENT_TYPE0 &&
+            &n= bsp;            = ;  hdcp_work->encryption_status[conn_index] <=3D MOD_HDCP_ENCRYP= TION_STATUS_HDCP2_TYPE0_ON)
+            &n= bsp;            = ;      drm_hdcp_update_content_protection(connecto= r, DRM_MODE_CONTENT_PROTECTION_ENABLED);
+            &n= bsp;          else if (conn_st= ate->hdcp_content_type =3D=3D DRM_MODE_HDCP_CONTENT_TYPE1 &&
+            &n= bsp;            = ;       hdcp_work->encryption_status[conn_= index] =3D=3D MOD_HDCP_ENCRYPTION_STATUS_HDCP2_TYPE1_ON)
+            &n= bsp;            = ;      drm_hdcp_update_content_protection(connecto= r, DRM_MODE_CONTENT_PROTECTION_ENABLED);
+            &n= bsp;  } else {
+            &n= bsp;          drm_hdcp_update_= content_protection(connector, DRM_MODE_CONTENT_PROTECTION_DESIRED);
+            &n= bsp;  }
 
+       }
 
         mutex_unlock(&hdcp_wor= k->mutex);
         drm_modeset_unlock(&de= v->mode_config.connection_mutex);
@@ -332,19 +366,28 @@ static void event_property_validate(struct work_struc= t *work)
         struct hdcp_workqueue *hdc= p_work =3D
            &nb= sp;    container_of(to_delayed_work(work), struct hdcp_workq= ueue, property_validate_dwork);
         struct mod_hdcp_display_qu= ery query;
-       struct amdgpu_dm_connector *aconnecto= r =3D hdcp_work->aconnector;
-
-       if (!aconnector)
-            &n= bsp;  return;
+       struct amdgpu_dm_connector *aconnecto= r;
+       unsigned int conn_index;
 
         mutex_lock(&hdcp_work-= >mutex);
 
-       query.encryption_status =3D MOD_HDCP_= ENCRYPTION_STATUS_HDCP_OFF;
-       mod_hdcp_query_display(&hdcp_work= ->hdcp, aconnector->base.index, &query);
+       for (conn_index =3D 0; conn_index <= ; MAX_NUM_OF_DISPLAYS; ++conn_index) {
+            &n= bsp;  aconnector =3D hdcp_work->aconnector[conn_index];
+
+            &n= bsp;  if (!aconnector)
+            &n= bsp;          continue;
+
+            &n= bsp;  query.encryption_status =3D MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF;=
+            &n= bsp;  mod_hdcp_query_display(&hdcp_work->hdcp, aconnector->b= ase.index, &query);
 
-       if (query.encryption_status !=3D hdcp= _work->encryption_status) {
-            &n= bsp;  hdcp_work->encryption_status =3D query.encryption_status;
-            &n= bsp;  schedule_work(&hdcp_work->property_update_work);
+            &n= bsp;  pr_debug("[HDCP_DM] display %d, CP %u, (query->enc_st, w= ork->enc_st): (%d, %d)\n",
+            &n= bsp;           aconnector= ->base.index, aconnector->base.state->content_protection,
+            &n= bsp;           query.encr= yption_status, hdcp_work->encryption_status[conn_index]);
+
+            &n= bsp;  if (query.encryption_status !=3D hdcp_work->encryption_status= [conn_index]) {
+            &n= bsp;          hdcp_work->en= cryption_status[conn_index] =3D query.encryption_status;
+            &n= bsp;          schedule_work(&a= mp;hdcp_work->property_update_work);
+            &n= bsp;  }
         }
 
         mutex_unlock(&hdcp_wor= k->mutex);
@@ -655,6 +698,10 @@ struct hdcp_workqueue *hdcp_create_workqueue(struct am= dgpu_device *adev, struct
            &nb= sp;    hdcp_work[i].hdcp.config.ddc.funcs.read_i2c =3D lp_re= ad_i2c;
            &nb= sp;    hdcp_work[i].hdcp.config.ddc.funcs.write_dpcd =3D lp_= write_dpcd;
            &nb= sp;    hdcp_work[i].hdcp.config.ddc.funcs.read_dpcd =3D lp_r= ead_dpcd;
+
+            &n= bsp;  memset(hdcp_work[i].aconnector, 0, sizeof(struct amdgpu_dm_conne= ctor *) * MAX_NUM_OF_DISPLAYS);
+            &n= bsp;  memset(hdcp_work[i].encryption_status, 0,
+            &n= bsp;          sizeof(enum mod_= hdcp_encryption_status) * MAX_NUM_OF_DISPLAYS);
         }
 
         cp_psp->funcs.update_st= ream_config =3D update_config;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h b/drive= rs/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
index 09294ff122fe..570863160d60 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2019 Advanced Micro Devices, Inc.
+ * Copyright (C) 2019-2020 Advanced Micro Devices, Inc. All rights reserve= d.
  *
  * Permission is hereby granted, free of charge, to any person obtain= ing a
  * copy of this software and associated documentation files (the &quo= t;Software"),
@@ -43,7 +43,7 @@ struct hdcp_workqueue {
         struct delayed_work callba= ck_dwork;
         struct delayed_work watchd= og_timer_dwork;
         struct delayed_work proper= ty_validate_dwork;
-       struct amdgpu_dm_connector *aconnecto= r;
+       struct amdgpu_dm_connector *aconnecto= r[MAX_NUM_OF_DISPLAYS];
         struct mutex mutex;
 
         struct mod_hdcp hdcp;
@@ -51,7 +51,7 @@ struct hdcp_workqueue {
         struct mod_hdcp_display di= splay;
         struct mod_hdcp_link link;=
 
-       enum mod_hdcp_encryption_status encry= ption_status;
+       enum mod_hdcp_encryption_status encry= ption_status[MAX_NUM_OF_DISPLAYS];
         uint8_t max_link;
 
         uint8_t *srm;
--
2.31.1

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