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From: "Liu, Monk" <Monk.Liu@amd.com>
To: "Wan, Gavin" <Gavin.Wan@amd.com>, Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
Date: Tue, 26 May 2020 04:35:04 +0000	[thread overview]
Message-ID: <DM5PR12MB1708EEBF8C63692DC3A1E75384B00@DM5PR12MB1708.namprd12.prod.outlook.com> (raw)
In-Reply-To: <DM6PR12MB41219812A4B209595F9DA352FCB40@DM6PR12MB4121.namprd12.prod.outlook.com>

This one looks better

You can put my RB 

Thanks 

_____________________________________
Monk Liu|GPU Virtualization Team |AMD


-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Wan, Gavin
Sent: Saturday, May 23, 2020 3:41 AM
To: Alex Deucher <alexdeucher@gmail.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.

HI Alex,

I fixed it as your suggestion.

Thanks,
Gavin

-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Friday, May 22, 2020 3:11 PM
To: Wan, Gavin <Gavin.Wan@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.

On Fri, May 22, 2020 at 2:20 PM Gavin Wan <Gavin.Wan@amd.com> wrote:
>
> For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side.
> The Guest should not program CP_INT_CNTL_RING0 again.
>
> Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
> Signed-off-by: Gavin Wan <Gavin.Wan@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index bd5dd4f64311..39275bf79448 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct 
> amdgpu_device *adev)  static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
>                                                bool enable)  {
> +       if (amdgpu_sriov_vf(adev))
> +               return;
> +

This needs to be below the stack variable declarations or you'll get a warning.

Alex

>         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
>
>         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, 
> CNTX_BUSY_INT_ENABLE,
> --
> 2.25.1
>
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  reply	other threads:[~2020-05-26  4:35 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-22 18:19 [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV Gavin Wan
2020-05-22 19:10 ` Alex Deucher
2020-05-22 19:40   ` Wan, Gavin
2020-05-26  4:35     ` Liu, Monk [this message]
  -- strict thread matches above, loose matches on Subject: below --
2020-05-22 19:39 Gavin Wan
2020-05-22 19:52 ` Alex Deucher
2020-05-21 19:53 Gavin Wan
2020-05-21 20:25 ` Alex Deucher
2020-05-22  3:40 ` Liu, Monk
2020-05-22  3:46 ` Chen, Guchun
2020-05-22  5:09   ` Zhang, Hawking
2020-05-22  5:51     ` Liu, Monk
2020-05-22  6:12       ` Liu, Monk
2020-05-22  6:16         ` Zhang, Hawking
2020-05-22  6:16           ` Zhang, Hawking
2020-05-22 18:23             ` Wan, Gavin

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