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boundary="===============1371727078==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============1371727078== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_DM6PR12MB2939FC23A4404409980F7D1AFB4D9DM6PR12MB2939namp_" --_000_DM6PR12MB2939FC23A4404409980F7D1AFB4D9DM6PR12MB2939namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Public Use] Inline. From: Bas Nieuwenhuizen Sent: Thursday, April 15, 2021 7:26 AM To: Zhuo, Qingqing Cc: amd-gfx mailing list ; Mark Yacoub ; Deucher, Alexander ; Wheel= er, Daniel ; Siqueira, Rodrigo ; Kazlauskas, Nicholas Subject: Re: [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3 On Thu, Apr 15, 2021 at 1:35 AM Qingqing Zhuo > wrote: [Why] Current list only includes modifiers where DCC_MAX_COMPRESSED_BLOCK is set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B is also supported and used by userspace. [How] Add AMD_FMT_MOD_DCC_BLOCK_64B to modifiers with DCC supported. Signed-off-by: Qingqing Zhuo > --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e29cb2e956db..c3cbc3d298e7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4535,6 +4535,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *ad= ev, int pipe_xor_bits =3D ilog2(adev->gfx.config.gb_addr_config_fields.= num_pipes); int pkrs =3D ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)= ; + add_modifier(mods, size, capacity, AMD_FMT_MOD | + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX1= 0_RBPLUS) | + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | + AMD_FMT_MOD_SET(PACKERS, pkrs) | + AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_D= CC_BLOCK_64B)); Thanks for finding this issue. Looking at it it looks to me like the origin= al entries are mistaken. Can we just change the DCC_MAX_COMPRESSED_BLOCK i= n the already existing DCC entries? Looks like Mesa always uses the AMD_FMT= _MOD_DCC_BLOCK_64B anyway, and I don't think DCC_INDEPENDENT_64B=3D1 + DCC_= MAX_COMPRESSED_BLOCK=3DAMD_FMT_MOD_DCC_BLOCK_128B makes sense. Thanks for the suggestion. Will send out an updated version soon. + add_modifier(mods, size, capacity, AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX1= 0_RBPLUS) | @@ -4546,6 +4557,18 @@ add_gfx10_3_modifiers(const struct amdgpu_device *ad= ev, AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_D= CC_BLOCK_128B)); + add_modifier(mods, size, capacity, AMD_FMT_MOD | + AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | + AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX1= 0_RBPLUS) | + AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) | + AMD_FMT_MOD_SET(PACKERS, pkrs) | + AMD_FMT_MOD_SET(DCC, 1) | + AMD_FMT_MOD_SET(DCC_RETILE, 1) | + AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) | + AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) | + AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_D= CC_BLOCK_64B)); + add_modifier(mods, size, capacity, AMD_FMT_MOD | AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX1= 0_RBPLUS) | -- 2.17.1 --_000_DM6PR12MB2939FC23A4404409980F7D1AFB4D9DM6PR12MB2939namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Publ= ic Use]

 

Inline.

 

From: Bas Nieuwenhuizen <bas@basnieuwenhui= zen.nl>
Sent: Thursday, April 15, 2021 7:26 AM
To: Zhuo, Qingqing <Qingqing.Zhuo@amd.com>
Cc: amd-gfx mailing list <amd-gfx@lists.freedesktop.org>; Mark= Yacoub <markyacoub@chromium.org>; Deucher, Alexander <Alexander.D= eucher@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Siqueir= a, Rodrigo <Rodrigo.Siqueira@amd.com>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>
Subject: Re: [PATCH 1/2] drm/amd/display: Update modifier list for g= fx10_3

 

 

 

On Thu, Apr 15, 2021 at 1:35 AM Qingqing Zhuo <qingqing.zhuo@amd.com> wrote:=

[Why]
Current list only includes modifiers where DCC_MAX_COMPRESSED_BLOCK
is set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B
is also supported and used by userspace.

[How]
Add AMD_FMT_MOD_DCC_BLOCK_64B to modifiers with DCC supported.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++++++++++++++++++= +
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gp= u/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e29cb2e956db..c3cbc3d298e7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4535,6 +4535,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *ad= ev,
        int pipe_xor_bits =3D ilog2(adev->gfx.config= .gb_addr_config_fields.num_pipes);
        int pkrs =3D ilog2(adev->gfx.config.gb_addr_= config_fields.num_pkrs);

+       add_modifier(mods, size, capacity, AMD_FMT_MOD = |
+                   AMD_F= MT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+                   AMD_F= MT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+                   AMD_F= MT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+                   AMD_F= MT_MOD_SET(PACKERS, pkrs) |
+                   AMD_F= MT_MOD_SET(DCC, 1) |
+                   AMD_F= MT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+                   AMD_F= MT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+                   AMD_F= MT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+                   AMD_F= MT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));

 

Thanks for finding this issue. Looking at it it look= s to me like the original entries are mistaken. Can we just change the = ; DCC_MAX_COMPRESSED_BLOCK in the already existing DCC entries? Looks like = Mesa always uses the AMD_FMT_MOD_DCC_BLOCK_64B anyway, and I don't think DCC_INDEPENDENT_64B=3D1 + DCC_MAX_COMPRESSED_BLO= CK=3DAMD_FMT_MOD_DCC_BLOCK_128B makes sense.

 

Thanks for the suggest= ion. Will send out an updated version soon.

 

+
        add_modifier(mods, size, capacity, AMD_FMT_MOD = |
                    AMD_F= MT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
                    AMD_F= MT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
@@ -4546,6 +4557,18 @@ add_gfx10_3_modifiers(const struct amdgpu_device *ad= ev,
                    AMD_F= MT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
                    AMD_F= MT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));

+       add_modifier(mods, size, capacity, AMD_FMT_MOD = |
+                   AMD_F= MT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+                   AMD_F= MT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+                   AMD_F= MT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+                   AMD_F= MT_MOD_SET(PACKERS, pkrs) |
+                   AMD_F= MT_MOD_SET(DCC, 1) |
+                   AMD_F= MT_MOD_SET(DCC_RETILE, 1) |
+                   AMD_F= MT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+                   AMD_F= MT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+                   AMD_F= MT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+                   AMD_F= MT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
+
        add_modifier(mods, size, capacity, AMD_FMT_MOD = |
                    AMD_F= MT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
                    AMD_F= MT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
--
2.17.1

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