AMD-GFX Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings
@ 2020-06-22 22:12 Alex Deucher
  2020-06-24 14:19 ` Alex Deucher
  0 siblings, 1 reply; 4+ messages in thread
From: Alex Deucher @ 2020-06-22 22:12 UTC (permalink / raw)
  To: amd-gfx; +Cc: Alex Deucher

drop the duplicate register macros from sid.h and use the
standard ones in the oss register headers.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/si.c    |  1 +
 drivers/gpu/drm/amd/amdgpu/si_ih.c |  2 ++
 drivers/gpu/drm/amd/amdgpu/sid.h   | 19 -------------------
 3 files changed, 3 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index cda9aa5e4b9e..9b12285177e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -45,6 +45,7 @@
 #include "dce_virtual.h"
 #include "gca/gfx_6_0_d.h"
 #include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
 #include "gmc/gmc_6_0_d.h"
 #include "dce/dce_6_0_d.h"
 #include "uvd/uvd_4_0_d.h"
diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index 88ae27a5a03d..621727d7fd18 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -27,6 +27,8 @@
 #include "amdgpu_ih.h"
 #include "sid.h"
 #include "si_ih.h"
+#include "oss/oss_1_0_d.h"
+#include "oss/oss_1_0_sh_mask.h"
 
 static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
index 75b5d441b628..5f660f0c819f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sid.h
+++ b/drivers/gpu/drm/amd/amdgpu/sid.h
@@ -2341,11 +2341,6 @@
 #       define NI_INPUT_GAMMA_XVYCC_222                3
 #       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) & 0x3) << 4)
 
-#define IH_RB_WPTR__RB_OVERFLOW_MASK	0x1
-#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
-#define SRBM_STATUS__IH_BUSY_MASK	0x20000
-#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK	0x400
-
 #define	BLACKOUT_MODE_MASK			0x00000007
 #define	VGA_RENDER_CONTROL			0xC0
 #define R_000300_VGA_RENDER_CONTROL             0xC0
@@ -2432,18 +2427,6 @@
 #define MC_SEQ_MISC0__MT__HBM    0x60000000
 #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
 
-#define SRBM_STATUS__MCB_BUSY_MASK 0x200
-#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
-#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
-#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
-#define SRBM_STATUS__MCC_BUSY_MASK 0x800
-#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
-#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
-#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
-#define SRBM_STATUS__VMC_BUSY_MASK 0x100
-#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
-
-
 #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
 #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
 #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
@@ -2468,8 +2451,6 @@
 
 #define PCIE_BUS_CLK    10000
 #define TCLK            (PCIE_BUS_CLK / 10)
-#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK		0xf0000000
-#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
 #define	PCIE_PORT_INDEX					0xe
 #define	PCIE_PORT_DATA					0xf
 #define EVERGREEN_PIF_PHY0_INDEX                        0x8
-- 
2.25.4

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings
  2020-06-22 22:12 [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings Alex Deucher
@ 2020-06-24 14:19 ` Alex Deucher
  2020-06-24 14:23   ` Christian König
  2020-06-24 14:24   ` Zhang, Hawking
  0 siblings, 2 replies; 4+ messages in thread
From: Alex Deucher @ 2020-06-24 14:19 UTC (permalink / raw)
  To: amd-gfx list; +Cc: Alex Deucher

Ping?

On Mon, Jun 22, 2020 at 6:12 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> drop the duplicate register macros from sid.h and use the
> standard ones in the oss register headers.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/si.c    |  1 +
>  drivers/gpu/drm/amd/amdgpu/si_ih.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/sid.h   | 19 -------------------
>  3 files changed, 3 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
> index cda9aa5e4b9e..9b12285177e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -45,6 +45,7 @@
>  #include "dce_virtual.h"
>  #include "gca/gfx_6_0_d.h"
>  #include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
>  #include "gmc/gmc_6_0_d.h"
>  #include "dce/dce_6_0_d.h"
>  #include "uvd/uvd_4_0_d.h"
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 88ae27a5a03d..621727d7fd18 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -27,6 +27,8 @@
>  #include "amdgpu_ih.h"
>  #include "sid.h"
>  #include "si_ih.h"
> +#include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
>
>  static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
> index 75b5d441b628..5f660f0c819f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/sid.h
> @@ -2341,11 +2341,6 @@
>  #       define NI_INPUT_GAMMA_XVYCC_222                3
>  #       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) & 0x3) << 4)
>
> -#define IH_RB_WPTR__RB_OVERFLOW_MASK   0x1
> -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
> -#define SRBM_STATUS__IH_BUSY_MASK      0x20000
> -#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK    0x400
> -
>  #define        BLACKOUT_MODE_MASK                      0x00000007
>  #define        VGA_RENDER_CONTROL                      0xC0
>  #define R_000300_VGA_RENDER_CONTROL             0xC0
> @@ -2432,18 +2427,6 @@
>  #define MC_SEQ_MISC0__MT__HBM    0x60000000
>  #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
>
> -#define SRBM_STATUS__MCB_BUSY_MASK 0x200
> -#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
> -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
> -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
> -#define SRBM_STATUS__MCC_BUSY_MASK 0x800
> -#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
> -#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
> -#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
> -#define SRBM_STATUS__VMC_BUSY_MASK 0x100
> -#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
> -
> -
>  #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
>  #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
>  #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
> @@ -2468,8 +2451,6 @@
>
>  #define PCIE_BUS_CLK    10000
>  #define TCLK            (PCIE_BUS_CLK / 10)
> -#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK              0xf0000000
> -#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
>  #define        PCIE_PORT_INDEX                                 0xe
>  #define        PCIE_PORT_DATA                                  0xf
>  #define EVERGREEN_PIF_PHY0_INDEX                        0x8
> --
> 2.25.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings
  2020-06-24 14:19 ` Alex Deucher
@ 2020-06-24 14:23   ` Christian König
  2020-06-24 14:24   ` Zhang, Hawking
  1 sibling, 0 replies; 4+ messages in thread
From: Christian König @ 2020-06-24 14:23 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx list; +Cc: Alex Deucher

Acked-by: Christian König <christian.koenig@amd.com>

Am 24.06.20 um 16:19 schrieb Alex Deucher:
> Ping?
>
> On Mon, Jun 22, 2020 at 6:12 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>> drop the duplicate register macros from sid.h and use the
>> standard ones in the oss register headers.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/si.c    |  1 +
>>   drivers/gpu/drm/amd/amdgpu/si_ih.c |  2 ++
>>   drivers/gpu/drm/amd/amdgpu/sid.h   | 19 -------------------
>>   3 files changed, 3 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
>> index cda9aa5e4b9e..9b12285177e3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
>> @@ -45,6 +45,7 @@
>>   #include "dce_virtual.h"
>>   #include "gca/gfx_6_0_d.h"
>>   #include "oss/oss_1_0_d.h"
>> +#include "oss/oss_1_0_sh_mask.h"
>>   #include "gmc/gmc_6_0_d.h"
>>   #include "dce/dce_6_0_d.h"
>>   #include "uvd/uvd_4_0_d.h"
>> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> index 88ae27a5a03d..621727d7fd18 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
>> @@ -27,6 +27,8 @@
>>   #include "amdgpu_ih.h"
>>   #include "sid.h"
>>   #include "si_ih.h"
>> +#include "oss/oss_1_0_d.h"
>> +#include "oss/oss_1_0_sh_mask.h"
>>
>>   static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h
>> index 75b5d441b628..5f660f0c819f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/sid.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/sid.h
>> @@ -2341,11 +2341,6 @@
>>   #       define NI_INPUT_GAMMA_XVYCC_222                3
>>   #       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) & 0x3) << 4)
>>
>> -#define IH_RB_WPTR__RB_OVERFLOW_MASK   0x1
>> -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
>> -#define SRBM_STATUS__IH_BUSY_MASK      0x20000
>> -#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK    0x400
>> -
>>   #define        BLACKOUT_MODE_MASK                      0x00000007
>>   #define        VGA_RENDER_CONTROL                      0xC0
>>   #define R_000300_VGA_RENDER_CONTROL             0xC0
>> @@ -2432,18 +2427,6 @@
>>   #define MC_SEQ_MISC0__MT__HBM    0x60000000
>>   #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
>>
>> -#define SRBM_STATUS__MCB_BUSY_MASK 0x200
>> -#define SRBM_STATUS__MCB_BUSY__SHIFT 0x9
>> -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400
>> -#define SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa
>> -#define SRBM_STATUS__MCC_BUSY_MASK 0x800
>> -#define SRBM_STATUS__MCC_BUSY__SHIFT 0xb
>> -#define SRBM_STATUS__MCD_BUSY_MASK 0x1000
>> -#define SRBM_STATUS__MCD_BUSY__SHIFT 0xc
>> -#define SRBM_STATUS__VMC_BUSY_MASK 0x100
>> -#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
>> -
>> -
>>   #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000
>>   #define CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000
>>   #define CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000
>> @@ -2468,8 +2451,6 @@
>>
>>   #define PCIE_BUS_CLK    10000
>>   #define TCLK            (PCIE_BUS_CLK / 10)
>> -#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK              0xf0000000
>> -#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
>>   #define        PCIE_PORT_INDEX                                 0xe
>>   #define        PCIE_PORT_DATA                                  0xf
>>   #define EVERGREEN_PIF_PHY0_INDEX                        0x8
>> --
>> 2.25.4
>>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

* RE: [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings
  2020-06-24 14:19 ` Alex Deucher
  2020-06-24 14:23   ` Christian König
@ 2020-06-24 14:24   ` Zhang, Hawking
  1 sibling, 0 replies; 4+ messages in thread
From: Zhang, Hawking @ 2020-06-24 14:24 UTC (permalink / raw)
  To: Alex Deucher, amd-gfx list; +Cc: Deucher, Alexander

[AMD Public Use]

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Wednesday, June 24, 2020 22:20
To: amd-gfx list <amd-gfx@lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings

Ping?

On Mon, Jun 22, 2020 at 6:12 PM Alex Deucher <alexdeucher@gmail.com> wrote:
>
> drop the duplicate register macros from sid.h and use the standard 
> ones in the oss register headers.
>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/si.c    |  1 +
>  drivers/gpu/drm/amd/amdgpu/si_ih.c |  2 ++
>  drivers/gpu/drm/amd/amdgpu/sid.h   | 19 -------------------
>  3 files changed, 3 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/si.c 
> b/drivers/gpu/drm/amd/amdgpu/si.c index cda9aa5e4b9e..9b12285177e3 
> 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si.c
> @@ -45,6 +45,7 @@
>  #include "dce_virtual.h"
>  #include "gca/gfx_6_0_d.h"
>  #include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
>  #include "gmc/gmc_6_0_d.h"
>  #include "dce/dce_6_0_d.h"
>  #include "uvd/uvd_4_0_d.h"
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c 
> b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> index 88ae27a5a03d..621727d7fd18 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
> @@ -27,6 +27,8 @@
>  #include "amdgpu_ih.h"
>  #include "sid.h"
>  #include "si_ih.h"
> +#include "oss/oss_1_0_d.h"
> +#include "oss/oss_1_0_sh_mask.h"
>
>  static void si_ih_set_interrupt_funcs(struct amdgpu_device *adev);
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h 
> b/drivers/gpu/drm/amd/amdgpu/sid.h
> index 75b5d441b628..5f660f0c819f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sid.h
> +++ b/drivers/gpu/drm/amd/amdgpu/sid.h
> @@ -2341,11 +2341,6 @@
>  #       define NI_INPUT_GAMMA_XVYCC_222                3
>  #       define NI_OVL_INPUT_GAMMA_MODE(x)              (((x) & 0x3) << 4)
>
> -#define IH_RB_WPTR__RB_OVERFLOW_MASK   0x1
> -#define IH_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK 0x80000000
> -#define SRBM_STATUS__IH_BUSY_MASK      0x20000
> -#define SRBM_SOFT_RESET__SOFT_RESET_IH_MASK    0x400
> -
>  #define        BLACKOUT_MODE_MASK                      0x00000007
>  #define        VGA_RENDER_CONTROL                      0xC0
>  #define R_000300_VGA_RENDER_CONTROL             0xC0
> @@ -2432,18 +2427,6 @@
>  #define MC_SEQ_MISC0__MT__HBM    0x60000000
>  #define MC_SEQ_MISC0__MT__DDR3   0xB0000000
>
> -#define SRBM_STATUS__MCB_BUSY_MASK 0x200 -#define 
> SRBM_STATUS__MCB_BUSY__SHIFT 0x9 -#define 
> SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK 0x400 -#define 
> SRBM_STATUS__MCB_NON_DISPLAY_BUSY__SHIFT 0xa -#define 
> SRBM_STATUS__MCC_BUSY_MASK 0x800 -#define SRBM_STATUS__MCC_BUSY__SHIFT 
> 0xb -#define SRBM_STATUS__MCD_BUSY_MASK 0x1000 -#define 
> SRBM_STATUS__MCD_BUSY__SHIFT 0xc -#define SRBM_STATUS__VMC_BUSY_MASK 
> 0x100 -#define SRBM_STATUS__VMC_BUSY__SHIFT 0x8
> -
> -
>  #define GRBM_STATUS__GUI_ACTIVE_MASK 0x80000000  #define 
> CP_INT_CNTL_RING__TIME_STAMP_INT_ENABLE_MASK 0x4000000  #define 
> CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK 0x800000 @@ -2468,8 
> +2451,6 @@
>
>  #define PCIE_BUS_CLK    10000
>  #define TCLK            (PCIE_BUS_CLK / 10)
> -#define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK              0xf0000000
> -#define CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT 0x1c
>  #define        PCIE_PORT_INDEX                                 0xe
>  #define        PCIE_PORT_DATA                                  0xf
>  #define EVERGREEN_PIF_PHY0_INDEX                        0x8
> --
> 2.25.4
>
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Chawking.zhang%40amd.com%7C4fec5ee61df24949a27908d81849a8f9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637286051966961153&amp;sdata=VbX%2BkPjTQyWhFuoDGYLxmlmJtbD1xnsWOMX0GFsr3To%3D&amp;reserved=0
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, back to index

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-22 22:12 [PATCH] drm/amdgpu/uvd3.x: fix register definition warnings Alex Deucher
2020-06-24 14:19 ` Alex Deucher
2020-06-24 14:23   ` Christian König
2020-06-24 14:24   ` Zhang, Hawking

AMD-GFX Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/amd-gfx/0 amd-gfx/git/0.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 amd-gfx amd-gfx/ https://lore.kernel.org/amd-gfx \
		amd-gfx@lists.freedesktop.org
	public-inbox-index amd-gfx

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.freedesktop.lists.amd-gfx


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git