* [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. @ 2020-05-22 18:19 Gavin Wan 2020-05-22 19:10 ` Alex Deucher 0 siblings, 1 reply; 16+ messages in thread From: Gavin Wan @ 2020-05-22 18:19 UTC (permalink / raw) To: amd-gfx; +Cc: Gavin Wan For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. The Guest should not program CP_INT_CNTL_RING0 again. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..39275bf79448 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 18:19 [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV Gavin Wan @ 2020-05-22 19:10 ` Alex Deucher 2020-05-22 19:40 ` Wan, Gavin 0 siblings, 1 reply; 16+ messages in thread From: Alex Deucher @ 2020-05-22 19:10 UTC (permalink / raw) To: Gavin Wan; +Cc: amd-gfx list On Fri, May 22, 2020 at 2:20 PM Gavin Wan <Gavin.Wan@amd.com> wrote: > > For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. > The Guest should not program CP_INT_CNTL_RING0 again. > > Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 > Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index bd5dd4f64311..39275bf79448 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) > static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > bool enable) > { > + if (amdgpu_sriov_vf(adev)) > + return; > + This needs to be below the stack variable declarations or you'll get a warning. Alex > u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > > tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 19:10 ` Alex Deucher @ 2020-05-22 19:40 ` Wan, Gavin 2020-05-26 4:35 ` Liu, Monk 0 siblings, 1 reply; 16+ messages in thread From: Wan, Gavin @ 2020-05-22 19:40 UTC (permalink / raw) To: Alex Deucher; +Cc: amd-gfx list HI Alex, I fixed it as your suggestion. Thanks, Gavin -----Original Message----- From: Alex Deucher <alexdeucher@gmail.com> Sent: Friday, May 22, 2020 3:11 PM To: Wan, Gavin <Gavin.Wan@amd.com> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org> Subject: Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. On Fri, May 22, 2020 at 2:20 PM Gavin Wan <Gavin.Wan@amd.com> wrote: > > For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. > The Guest should not program CP_INT_CNTL_RING0 again. > > Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 > Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index bd5dd4f64311..39275bf79448 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct > amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > bool enable) { > + if (amdgpu_sriov_vf(adev)) > + return; > + This needs to be below the stack variable declarations or you'll get a warning. Alex > u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > > tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, > CNTX_BUSY_INT_ENABLE, > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CGa > vin.Wan%40amd.com%7C23c1770b248841c7032a08d7fe83d940%7C3dd8961fe4884e6 > 08e11a82d994e183d%7C0%7C0%7C637257714548695750&sdata=PaWH5hLNb3N1Z > lalw4GsjeeB46xzCVxXDWBROndcKsk%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 19:40 ` Wan, Gavin @ 2020-05-26 4:35 ` Liu, Monk 0 siblings, 0 replies; 16+ messages in thread From: Liu, Monk @ 2020-05-26 4:35 UTC (permalink / raw) To: Wan, Gavin, Alex Deucher; +Cc: amd-gfx list This one looks better You can put my RB Thanks _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Wan, Gavin Sent: Saturday, May 23, 2020 3:41 AM To: Alex Deucher <alexdeucher@gmail.com> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. HI Alex, I fixed it as your suggestion. Thanks, Gavin -----Original Message----- From: Alex Deucher <alexdeucher@gmail.com> Sent: Friday, May 22, 2020 3:11 PM To: Wan, Gavin <Gavin.Wan@amd.com> Cc: amd-gfx list <amd-gfx@lists.freedesktop.org> Subject: Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. On Fri, May 22, 2020 at 2:20 PM Gavin Wan <Gavin.Wan@amd.com> wrote: > > For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. > The Guest should not program CP_INT_CNTL_RING0 again. > > Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 > Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index bd5dd4f64311..39275bf79448 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct > amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > bool enable) { > + if (amdgpu_sriov_vf(adev)) > + return; > + This needs to be below the stack variable declarations or you'll get a warning. Alex > u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > > tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, > CNTX_BUSY_INT_ENABLE, > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist > s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7CGa > vin.Wan%40amd.com%7C23c1770b248841c7032a08d7fe83d940%7C3dd8961fe4884e6 > 08e11a82d994e183d%7C0%7C0%7C637257714548695750&sdata=PaWH5hLNb3N1Z > lalw4GsjeeB46xzCVxXDWBROndcKsk%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7Cc7ef193b2ceb418c3be608d7fe880de4%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257732654114415&sdata=2kIarekeuDY4gio%2F%2BKbQJsl8RbWrmPC9K1KnwopK5FM%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. @ 2020-05-22 19:39 Gavin Wan 2020-05-22 19:52 ` Alex Deucher 0 siblings, 1 reply; 16+ messages in thread From: Gavin Wan @ 2020-05-22 19:39 UTC (permalink / raw) To: amd-gfx; +Cc: Gavin Wan For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. The Guest should not program CP_INT_CNTL_RING0 again. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..4d6928cfc269 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); + u32 tmp; + + if (amdgpu_sriov_vf(adev)) + return; + + tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 19:39 Gavin Wan @ 2020-05-22 19:52 ` Alex Deucher 0 siblings, 0 replies; 16+ messages in thread From: Alex Deucher @ 2020-05-22 19:52 UTC (permalink / raw) To: Gavin Wan; +Cc: amd-gfx list On Fri, May 22, 2020 at 3:39 PM Gavin Wan <Gavin.Wan@amd.com> wrote: > > For SRIOV, since the CP_INT_CNTL_RING0 is programed on host side. > The Guest should not program CP_INT_CNTL_RING0 again. > > Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 > Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index bd5dd4f64311..4d6928cfc269 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4558,7 +4558,12 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) > static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > bool enable) > { > - u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > + u32 tmp; > + > + if (amdgpu_sriov_vf(adev)) > + return; > + > + tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > > tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, > enable ? 1 : 0); > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.
@ 2020-05-21 19:53 Gavin Wan
2020-05-21 20:25 ` Alex Deucher
` (2 more replies)
0 siblings, 3 replies; 16+ messages in thread
From: Gavin Wan @ 2020-05-21 19:53 UTC (permalink / raw)
To: amd-gfx; +Cc: Gavin Wan
For SRIOV, since the CGCG is set on host side. The Guest should
not program CGCG again.
The patch ignores setting CGCG for SRIOV.
Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1
Signed-off-by: Gavin Wan <Gavin.Wan@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index bd5dd4f64311..52b6e4759cf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
@@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* It is disabled by HW by default */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
/* 0 - Disable some blocks' MGCG */
@@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
{
uint32_t data, def;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
/* Enable 3D CGCG/CGLS */
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
/* write cmd to clear cgcg/cgls ov */
@@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
{
uint32_t def, data;
+ if (amdgpu_sriov_vf(adev))
+ return;
+
if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
/* unset CGCG override */
@@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
bool enable)
{
+ if (amdgpu_sriov_vf(adev))
+ return;
+
amdgpu_gfx_rlc_enter_safe_mode(adev);
if (enable) {
--
2.25.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-21 19:53 Gavin Wan @ 2020-05-21 20:25 ` Alex Deucher 2020-05-22 3:40 ` Liu, Monk 2020-05-22 3:46 ` Chen, Guchun 2 siblings, 0 replies; 16+ messages in thread From: Alex Deucher @ 2020-05-21 20:25 UTC (permalink / raw) To: Gavin Wan; +Cc: amd-gfx list On Thu, May 21, 2020 at 3:53 PM Gavin Wan <Gavin.Wan@amd.com> wrote: > > For SRIOV, since the CGCG is set on host side. The Guest should > not program CGCG again. > > The patch ignores setting CGCG for SRIOV. > > Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 > Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index bd5dd4f64311..52b6e4759cf3 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) > static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, > bool enable) > { > + if (amdgpu_sriov_vf(adev)) > + return; > + > u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); > > tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, > @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade > { > uint32_t data, def; > > + if (amdgpu_sriov_vf(adev)) > + return; > + > /* It is disabled by HW by default */ > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { > /* 0 - Disable some blocks' MGCG */ > @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, > { > uint32_t data, def; > > + if (amdgpu_sriov_vf(adev)) > + return; > + > /* Enable 3D CGCG/CGLS */ > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { > /* write cmd to clear cgcg/cgls ov */ > @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade > { > uint32_t def, data; > > + if (amdgpu_sriov_vf(adev)) > + return; > + > if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { > def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); > /* unset CGCG override */ > @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade > static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, > bool enable) > { > + if (amdgpu_sriov_vf(adev)) > + return; > + > amdgpu_gfx_rlc_enter_safe_mode(adev); > > if (enable) { > -- > 2.25.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-21 19:53 Gavin Wan 2020-05-21 20:25 ` Alex Deucher @ 2020-05-22 3:40 ` Liu, Monk 2020-05-22 3:46 ` Chen, Guchun 2 siblings, 0 replies; 16+ messages in thread From: Liu, Monk @ 2020-05-22 3:40 UTC (permalink / raw) To: Wan, Gavin, amd-gfx; +Cc: Wan, Gavin Reviewed-by: Monk Liu <monk.liu@amd.com> _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0539b7a16a5f488b7ddf08d7fdc09f30%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256876073183596&sdata=gIakEeKOfji3Z29RdDojiPDtCegcfcCvFP0%2FOVFeSaQ%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-21 19:53 Gavin Wan 2020-05-21 20:25 ` Alex Deucher 2020-05-22 3:40 ` Liu, Monk @ 2020-05-22 3:46 ` Chen, Guchun 2020-05-22 5:09 ` Zhang, Hawking 2 siblings, 1 reply; 16+ messages in thread From: Chen, Guchun @ 2020-05-22 3:46 UTC (permalink / raw) To: Wan, Gavin, amd-gfx; +Cc: Wan, Gavin [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cguchun.chen%40amd.com%7C0539b7a16a5f488b7ddf08d7fdc09f30%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637256876068046189&sdata=wMjQV6VwTBu8pCfQjXf39e1ffQSkQHKkZdXyWjue%2FJk%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 3:46 ` Chen, Guchun @ 2020-05-22 5:09 ` Zhang, Hawking 2020-05-22 5:51 ` Liu, Monk 0 siblings, 1 reply; 16+ messages in thread From: Zhang, Hawking @ 2020-05-22 5:09 UTC (permalink / raw) To: Chen, Guchun, Wan, Gavin, amd-gfx; +Cc: Wan, Gavin [AMD Public Use] Can we leverage existing CG flags to control this rather than add amdgpu_sriov_vf(adev) check everywhere? If GC CG feature is programmed by host. We can just mask out the following flags for guest driver case (amdgpu_sriov_vf(adev)). AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually add unnecessary sustaining effort. Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, Guchun Sent: Friday, May 22, 2020 11:47 To: Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Chawking.zhang%40amd.com%7Cab787c659a654d8e6f9c08d7fe02c725%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257160214567792&sdata=gTreRUn9%2Br1sS%2FrMEA7bJ630LusX1396szicn2ZDwrg%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Chawking.zhang%40amd.com%7Cab787c659a654d8e6f9c08d7fe02c725%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257160214577779&sdata=yVL3hqGTscc9HtIj6YHRxo113b0VO0rqtorm1blUa4U%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 5:09 ` Zhang, Hawking @ 2020-05-22 5:51 ` Liu, Monk 2020-05-22 6:12 ` Liu, Monk 0 siblings, 1 reply; 16+ messages in thread From: Liu, Monk @ 2020-05-22 5:51 UTC (permalink / raw) To: Zhang, Hawking, Chen, Guchun, Wan, Gavin, amd-gfx; +Cc: Wan, Gavin Sounds a good idea @Wan, Gavin can you try hawking's advice ? _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: Friday, May 22, 2020 1:09 PM To: Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Can we leverage existing CG flags to control this rather than add amdgpu_sriov_vf(adev) check everywhere? If GC CG feature is programmed by host. We can just mask out the following flags for guest driver case (amdgpu_sriov_vf(adev)). AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually add unnecessary sustaining effort. Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, Guchun Sent: Friday, May 22, 2020 11:47 To: Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C99086e3adedb45ad03ea08d7fe0e3fc9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257210092457510&sdata=ntHm%2Bgwj4Q9Tv30c1irg%2BWf7y9QxQUSTO4%2FWMhpjK6g%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C99086e3adedb45ad03ea08d7fe0e3fc9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257210092457510&sdata=ntHm%2Bgwj4Q9Tv30c1irg%2BWf7y9QxQUSTO4%2FWMhpjK6g%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C99086e3adedb45ad03ea08d7fe0e3fc9%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257210092457510&sdata=ntHm%2Bgwj4Q9Tv30c1irg%2BWf7y9QxQUSTO4%2FWMhpjK6g%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 5:51 ` Liu, Monk @ 2020-05-22 6:12 ` Liu, Monk 2020-05-22 6:16 ` Zhang, Hawking 0 siblings, 1 reply; 16+ messages in thread From: Liu, Monk @ 2020-05-22 6:12 UTC (permalink / raw) To: Liu, Monk, Zhang, Hawking, Chen, Guchun, Wan, Gavin, amd-gfx; +Cc: Wan, Gavin Gavin Looks the only place you need to change is the part of avoid touching "CP_INT_CNTL_RING0" which is handled by GIM now Others looks not needed at all _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Liu, Monk Sent: Friday, May 22, 2020 1:52 PM To: Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Sounds a good idea @Wan, Gavin can you try hawking's advice ? _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: Friday, May 22, 2020 1:09 PM To: Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Can we leverage existing CG flags to control this rather than add amdgpu_sriov_vf(adev) check everywhere? If GC CG feature is programmed by host. We can just mask out the following flags for guest driver case (amdgpu_sriov_vf(adev)). AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually add unnecessary sustaining effort. Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, Guchun Sent: Friday, May 22, 2020 11:47 To: Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 6:12 ` Liu, Monk @ 2020-05-22 6:16 ` Zhang, Hawking 2020-05-22 6:16 ` Zhang, Hawking 0 siblings, 1 reply; 16+ messages in thread From: Zhang, Hawking @ 2020-05-22 6:16 UTC (permalink / raw) To: Liu, Monk, Chen, Guchun, Wan, Gavin, amd-gfx; +Cc: Wan, Gavin [AMD Public Use] Yes, please try best effort to not introduce guest/one_vf/mult_vf check. Regards, Hawking -----Original Message----- From: Liu, Monk <Monk.Liu@amd.com> Sent: Friday, May 22, 2020 14:12 To: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Gavin Looks the only place you need to change is the part of avoid touching "CP_INT_CNTL_RING0" which is handled by GIM now Others looks not needed at all _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Liu, Monk Sent: Friday, May 22, 2020 1:52 PM To: Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Sounds a good idea @Wan, Gavin can you try hawking's advice ? _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: Friday, May 22, 2020 1:09 PM To: Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Can we leverage existing CG flags to control this rather than add amdgpu_sriov_vf(adev) check everywhere? If GC CG feature is programmed by host. We can just mask out the following flags for guest driver case (amdgpu_sriov_vf(adev)). AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually add unnecessary sustaining effort. Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, Guchun Sent: Friday, May 22, 2020 11:47 To: Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 6:16 ` Zhang, Hawking @ 2020-05-22 6:16 ` Zhang, Hawking 2020-05-22 18:23 ` Wan, Gavin 0 siblings, 1 reply; 16+ messages in thread From: Zhang, Hawking @ 2020-05-22 6:16 UTC (permalink / raw) To: Liu, Monk, Chen, Guchun, Wan, Gavin, amd-gfx; +Cc: Wan, Gavin [AMD Public Use] Or make it in more reasonable place. Regards, Hawking -----Original Message----- From: Zhang, Hawking Sent: Friday, May 22, 2020 14:16 To: Liu, Monk <Monk.Liu@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Yes, please try best effort to not introduce guest/one_vf/mult_vf check. Regards, Hawking -----Original Message----- From: Liu, Monk <Monk.Liu@amd.com> Sent: Friday, May 22, 2020 14:12 To: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Gavin Looks the only place you need to change is the part of avoid touching "CP_INT_CNTL_RING0" which is handled by GIM now Others looks not needed at all _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Liu, Monk Sent: Friday, May 22, 2020 1:52 PM To: Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Sounds a good idea @Wan, Gavin can you try hawking's advice ? _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: Friday, May 22, 2020 1:09 PM To: Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Can we leverage existing CG flags to control this rather than add amdgpu_sriov_vf(adev) check everywhere? If GC CG feature is programmed by host. We can just mask out the following flags for guest driver case (amdgpu_sriov_vf(adev)). AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually add unnecessary sustaining effort. Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, Guchun Sent: Friday, May 22, 2020 11:47 To: Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
* RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. 2020-05-22 6:16 ` Zhang, Hawking @ 2020-05-22 18:23 ` Wan, Gavin 0 siblings, 0 replies; 16+ messages in thread From: Wan, Gavin @ 2020-05-22 18:23 UTC (permalink / raw) To: Zhang, Hawking, Liu, Monk, Chen, Guchun, amd-gfx Fixed it as Monk and Hawking suggestion. Now it only has one checking in function gfx_v10_0_enable_gui_idle_interrupt. BTW, I update the commit, but it send out an another email. Thanks, Gavin -----Original Message----- From: Zhang, Hawking <Hawking.Zhang@amd.com> Sent: Friday, May 22, 2020 2:17 AM To: Liu, Monk <Monk.Liu@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Or make it in more reasonable place. Regards, Hawking -----Original Message----- From: Zhang, Hawking Sent: Friday, May 22, 2020 14:16 To: Liu, Monk <Monk.Liu@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Yes, please try best effort to not introduce guest/one_vf/mult_vf check. Regards, Hawking -----Original Message----- From: Liu, Monk <Monk.Liu@amd.com> Sent: Friday, May 22, 2020 14:12 To: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Gavin Looks the only place you need to change is the part of avoid touching "CP_INT_CNTL_RING0" which is handled by GIM now Others looks not needed at all _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Liu, Monk Sent: Friday, May 22, 2020 1:52 PM To: Zhang, Hawking <Hawking.Zhang@amd.com>; Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. Sounds a good idea @Wan, Gavin can you try hawking's advice ? _____________________________________ Monk Liu|GPU Virtualization Team |AMD -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking Sent: Friday, May 22, 2020 1:09 PM To: Chen, Guchun <Guchun.Chen@amd.com>; Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Can we leverage existing CG flags to control this rather than add amdgpu_sriov_vf(adev) check everywhere? If GC CG feature is programmed by host. We can just mask out the following flags for guest driver case (amdgpu_sriov_vf(adev)). AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS | AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS There are too many amdgpu_sriov_vf(adev) Check in amdgpu driver, which actually add unnecessary sustaining effort. Regards, Hawking -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Chen, Guchun Sent: Friday, May 22, 2020 11:47 To: Wan, Gavin <Gavin.Wan@amd.com>; amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: RE: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. [AMD Public Use] Please see one comment below. Regards, Guchun -----Original Message----- From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Gavin Wan Sent: Friday, May 22, 2020 3:53 AM To: amd-gfx@lists.freedesktop.org Cc: Wan, Gavin <Gavin.Wan@amd.com> Subject: [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV. For SRIOV, since the CGCG is set on host side. The Guest should not program CGCG again. The patch ignores setting CGCG for SRIOV. Change-Id: Ic336fab3b23b8371c9e9e192182a3ba14a8db8e1 Signed-off-by: Gavin Wan <Gavin.Wan@amd.com> --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index bd5dd4f64311..52b6e4759cf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4558,6 +4558,9 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev) static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + [Guchun]This coding style is not correct. You should put the check after the declare of 'u32 tmp'. Maybe it's better to split below line to declare and execution parts respectively. u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, @@ -6842,6 +6845,9 @@ static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *ade { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* It is disabled by HW by default */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) { /* 0 - Disable some blocks' MGCG */ @@ -6911,6 +6917,9 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev, { uint32_t data, def; + if (amdgpu_sriov_vf(adev)) + return; + /* Enable 3D CGCG/CGLS */ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) { /* write cmd to clear cgcg/cgls ov */ @@ -6953,6 +6962,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade { uint32_t def, data; + if (amdgpu_sriov_vf(adev)) + return; + if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) { def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE); /* unset CGCG override */ @@ -6994,6 +7006,9 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev, bool enable) { + if (amdgpu_sriov_vf(adev)) + return; + amdgpu_gfx_rlc_enter_safe_mode(adev); if (enable) { -- 2.25.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100002661&sdata=YG2D5uV7kD1mqPj3Bq8UicMrExQzyUaGIVJDxCryncE%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cmonk.liu%40amd.com%7C0bb2f0a4f21948486b3708d7fe14366a%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637257235100012654&sdata=E7p%2Fkc5qh%2BxIvjGM5dxJs5VuqGHvVIb%2FeNeDemis07Y%3D&reserved=0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-05-26 4:35 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-05-22 18:19 [PATCH] drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV Gavin Wan 2020-05-22 19:10 ` Alex Deucher 2020-05-22 19:40 ` Wan, Gavin 2020-05-26 4:35 ` Liu, Monk -- strict thread matches above, loose matches on Subject: below -- 2020-05-22 19:39 Gavin Wan 2020-05-22 19:52 ` Alex Deucher 2020-05-21 19:53 Gavin Wan 2020-05-21 20:25 ` Alex Deucher 2020-05-22 3:40 ` Liu, Monk 2020-05-22 3:46 ` Chen, Guchun 2020-05-22 5:09 ` Zhang, Hawking 2020-05-22 5:51 ` Liu, Monk 2020-05-22 6:12 ` Liu, Monk 2020-05-22 6:16 ` Zhang, Hawking 2020-05-22 6:16 ` Zhang, Hawking 2020-05-22 18:23 ` Wan, Gavin
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