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* [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish
@ 2021-04-19  8:47 Jiansong Chen
  2021-04-19  9:02 ` Zhou1, Tao
  0 siblings, 1 reply; 2+ messages in thread
From: Jiansong Chen @ 2021-04-19  8:47 UTC (permalink / raw)
  To: amd-gfx; +Cc: tao.zhou1, jack.gui, Jiansong Chen

dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Change-Id: I2c8f1022c0b4c5baf70d09ec99b7b2ca8da36bba
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 85a6a10e048f..49fd10a15707 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3377,7 +3377,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
-	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
+	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 	SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
-- 
2.25.1

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^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish
  2021-04-19  8:47 [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish Jiansong Chen
@ 2021-04-19  9:02 ` Zhou1, Tao
  0 siblings, 0 replies; 2+ messages in thread
From: Zhou1, Tao @ 2021-04-19  9:02 UTC (permalink / raw)
  To: Chen, Jiansong (Simon), amd-gfx; +Cc: Gui, Jack

[-- Attachment #1.1: Type: text/plain, Size: 1828 bytes --]

[AMD Official Use Only - Internal Distribution Only]

Reviewed-by: Tao Zhou <tao.zhou1@amd.com<mailto:tao.zhou1@amd.com>>
________________________________
From: Jiansong Chen <Jiansong.Chen@amd.com>
Sent: Monday, April 19, 2021 4:47 PM
To: amd-gfx@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Zhou1, Tao <Tao.Zhou1@amd.com>; Gui, Jack <Jack.Gui@amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen@amd.com>
Subject: [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish

dimgrey_cavefish has similar gc_10_3 ip with sienna_cichlid,
so follow its registers offset setting.

Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Change-Id: I2c8f1022c0b4c5baf70d09ec99b7b2ca8da36bba
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 85a6a10e048f..49fd10a15707 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3377,7 +3377,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
--
2.25.1


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https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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2021-04-19  8:47 [PATCH] drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish Jiansong Chen
2021-04-19  9:02 ` Zhou1, Tao

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