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boundary="===============0545430061==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0545430061== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB29579607351F120CB74BF527955A0MN2PR12MB2957namp_" --_000_MN2PR12MB29579607351F120CB74BF527955A0MN2PR12MB2957namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - Internal Distribution Only] Thanks Feifei! ________________________________ From: Xu, Feifei Sent: Wednesday, December 11, 2019 11:29 To: Yin, Tianci (Rico) ; amd-gfx@lists.freedesktop.org = Cc: Zhang, Hawking ; Yuan, Xiaojie ; Long, Gang ; Li, Pauline ; Yi= n, Tianci (Rico) Subject: RE: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings Series is Reviewed-by: Feifei Xu -----Original Message----- From: Tianci Yin Sent: Wednesday, December 11, 2019 11:22 AM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking ; Xu, Feifei ;= Yuan, Xiaojie ; Long, Gang ; Li, = Pauline ; Yin, Tianci (Rico) Subject: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings From: "Tianci.Yin" add registers: mmSPI_CONFIG_CNTL Signed-off-by: Tianci.Yin --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v10_0.c index ed630d37c32c..f3324fa4e194 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -114,6 +114,7 @@ static const struct soc15_reg_golden golden_settings_gc= _10_1[] =3D SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x044= 40000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff= 0f, 0x00000000), SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101)= , + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x0007= 0104), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xfff= fffff), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000= 130), SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xfff= fffff), -- 2.17.1 --_000_MN2PR12MB29579607351F120CB74BF527955A0MN2PR12MB2957namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only - Internal Distribution Only]


Thanks Feifei!
From: Xu, Feifei <Feifei= .Xu@amd.com>
Sent: Wednesday, December 11, 2019 11:29
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>; amd-gfx@lists.fre= edesktop.org <amd-gfx@lists.freedesktop.org>
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Yuan, Xiaojie <= Xiaojie.Yuan@amd.com>; Long, Gang <Gang.Long@amd.com>; Li, Pauline= <Pauline.Li@amd.com>; Yin, Tianci (Rico) <Tianci.Yin@amd.com><= br> Subject: RE: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden setting= s
 


Series is Reviewed-by: Feifei Xu <Feifei Xu@amd.com>

-----Original Message-----
From: Tianci Yin <tianci.yin@amd.com>
Sent: Wednesday, December 11, 2019 11:22 AM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Hawking <Hawking.Zhang@amd.com>; Xu, Feifei <Feifei.Xu@= amd.com>; Yuan, Xiaojie <Xiaojie.Yuan@amd.com>; Long, Gang <Gan= g.Long@amd.com>; Li, Pauline <Pauline.Li@amd.com>; Yin, Tianci (Ri= co) <Tianci.Yin@amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx10: update gfx golden settings

From: "Tianci.Yin" <tianci.yin@amd.com>

add registers: mmSPI_CONFIG_CNTL

Signed-off-by: Tianci.Yin <tianci.yin@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/a= mdgpu/gfx_v10_0.c
index ed630d37c32c..f3324fa4e194 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -114,6 +114,7 @@ static const struct soc15_reg_golden golden_setting= s_gc_10_1[] =3D
         SOC15_REG_GOLDEN_VALUE(GC,= 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
         SOC15_REG_GOLDEN_VALUE(GC,= 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
         SOC15_REG_GOLDEN_VALUE(GC,= 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmS= PI_CONFIG_CNTL, 0x001f0000, 0x00070104),
         SOC15_REG_GOLDEN_VALUE(GC,= 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
         SOC15_REG_GOLDEN_VALUE(GC,= 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
         SOC15_REG_GOLDEN_VALUE(GC,= 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
--
2.17.1

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