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boundary="===============0253556775==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0253556775== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB2957FD303FE96967B215F96E95370MN2PR12MB2957namp_" --_000_MN2PR12MB2957FD303FE96967B215F96E95370MN2PR12MB2957namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - Internal Distribution Only] Thanks Alex! ________________________________ From: Alex Deucher Sent: Wednesday, January 15, 2020 1:39 To: Yin, Tianci (Rico) Cc: amd-gfx list ; Xu, Feifei ; Zhang, Hawking Subject: Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden settings for n= avi14 On Tue, Jan 14, 2020 at 6:42 AM Tianci Yin wrote: > > From: "Tianci.Yin" > > remove registers: mmSPI_CONFIG_CNTL > add registers: mmSPI_CONFIG_CNTL_1 > > Change-Id: I0bbaeca184e7dc85463d6c5740151d6ba1b08c06 > Signed-off-by: Tianci.Yin Series is: Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd= /amdgpu/gfx_v10_0.c > index 4f6ffaf3f9be..3c9082b1eea9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -169,7 +169,7 @@ static const struct soc15_reg_golden golden_settings_= gc_10_1_1[] =3D > SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00= 000820), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000f= f0f, 0x00000000), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101= ), > - SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL, 0x001f0000, 0x00= 070105), > + SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x= 00070105), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xff= ffffff), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x0000= 0130), > SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xff= ffffff), > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists= .freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D02%7C01%7Ctianci= .yin%40amd.com%7Cced760baf9c0451c0e6708d79918b31c%7C3dd8961fe4884e608e11a82= d994e183d%7C0%7C0%7C637146203676595018&sdata=3DFJMr7sM3nIICn2hPyZCX851E= 4%2BCQxvY4U2pD6Rga6X4%3D&reserved=3D0 --_000_MN2PR12MB2957FD303FE96967B215F96E95370MN2PR12MB2957namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only - Internal Distribution Only]


Thanks Alex!
From: Alex Deucher <alex= deucher@gmail.com>
Sent: Wednesday, January 15, 2020 1:39
To: Yin, Tianci (Rico) <Tianci.Yin@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Xu, Feifei &= lt;Feifei.Xu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>
Subject: Re: [PATCH 2/2] drm/amdgpu/gfx10: update gfx golden setting= s for navi14
 
On Tue, Jan 14, 2020 at 6:42 AM Tianci Yin <tia= nci.yin@amd.com> wrote:
>
> From: "Tianci.Yin" <tianci.yin@amd.com>
>
> remove registers: mmSPI_CONFIG_CNTL
> add registers: mmSPI_CONFIG_CNTL_1
>
> Change-Id: I0bbaeca184e7dc85463d6c5740151d6ba1b08c06
> Signed-off-by: Tianci.Yin <tianci.yin@amd.com>

Series is:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/= amd/amdgpu/gfx_v10_0.c
> index 4f6ffaf3f9be..3c9082b1eea9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -169,7 +169,7 @@ static const struct soc15_reg_golden golden_se= ttings_gc_10_1_1[] =3D
>         SOC15_REG_GOLDEN_VALUE= (GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
>         SOC15_REG_GOLDEN_VALUE= (GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
>         SOC15_REG_GOLDEN_VALUE= (GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
> -       SOC15_REG_GOLDEN_VALUE(GC, 0, mm= SPI_CONFIG_CNTL, 0x001f0000, 0x00070105),
> +       SOC15_REG_GOLDEN_VALUE(GC, 0= , mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
>         SOC15_REG_GOLDEN_VALUE= (GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
>         SOC15_REG_GOLDEN_VALUE= (GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
>         SOC15_REG_GOLDEN_VALUE= (GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
> --
> 2.17.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists.f= reedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=3D02%7C01%7Ctian= ci.yin%40amd.com%7Cced760baf9c0451c0e6708d79918b31c%7C3dd8961fe4884e608e11a= 82d994e183d%7C0%7C0%7C637146203676595018&amp;sdata=3DFJMr7sM3nIICn2hPyZ= CX851E4%2BCQxvY4U2pD6Rga6X4%3D&amp;reserved=3D0
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